Sequential Wordline Erase Verify for 3D Memory Uniformity
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Solution Overview
Problem
In 3D replacement gate memory devices, there is a significant difference in erase speed across wordlines, leading to uneven erase depth and stress variations, which results in rapid degradation and poor data retention, as shallow and deep erased memory cells are not effectively verified during erase operations.
Innovation Solution
Implementing sequential wordline erase verify schemes that apply an inhibiting bias voltage to wordline groups based on their erase speed, allowing for independent verification and adjustment to prevent over-erase of faster cells while deeper erasing slower cells, thereby achieving uniform erase depth and reduced stress variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional erase operation is applied to all wordlines simultaneously, then the erase operation completes in a single step, but significant differences in erase speed across wordlines lead to uneven erase depth and stress variations
Solution Approach 1:
The patent segments the wordlines into multiple groups (first group and second group) and applies different erase verify schemes to each group. This segmentation allows independent control of erase operations for fast-erasing and slow-erasing wordline groups, resolving the contradiction between overall erase speed and uniformity by treating different segments differently based on their erase characteristics.
Solution Approach 2:
The patent applies local quality by implementing different erase verify strategies for different wordline groups. The first group of wordlines (faster erasing) receives one erase verify treatment while the second group of wordlines (slower erasing) receives a different treatment. This localized approach ensures each group achieves optimal erase depth uniformity according to its specific erase speed characteristics.
2Device complexity
If erase verify is performed on all wordlines uniformly, then verification is simplified, but shallow and deep erased memory cells are not effectively verified leading to rapid degradation
Solution Approach 1:
The verify scheme is segmented into different verification procedures for different wordline groups. The first group undergoes one verification process while the second group undergoes a different verification process, allowing each group to be verified according to its specific erase characteristics, thereby improving reliability without excessive complexity.
Solution Approach 2:
Different verification qualities are applied locally to different wordline groups. The first group of wordlines receives a verification treatment optimized for faster erasure, while the second group receives treatment optimized for slower erasure. This ensures that both shallow and deep erased cells are effectively verified, improving data retention while maintaining manageable complexity through targeted local optimizations.
3Manufacturing precision
If higher erase stress is applied to achieve deeper erasure, then slower-erasing wordlines can be erased more effectively, but faster-erasing cells become over-erased and degraded
Solution Approach 1:
The patent segments wordlines into groups that can tolerate different erase stress levels. The first group (faster erasing) is subjected to lower erase stress to prevent over-erasure and degradation, while the second group (slower erasing) is subjected to higher erase stress to achieve adequate erase depth. This segmentation resolves the contradiction by allowing differentiated stress application.
Solution Approach 2:
Different erase stress qualities are applied locally to different wordline groups. The first group receives a milder erase treatment appropriate for its faster erasure characteristics, while the second group receives a stronger erase treatment appropriate for its slower erasure characteristics. This local differentiation ensures adequate erase depth for all cells without causing over-erasure degradation.
Data Source
AI summary
A memory device includes a memory array including a plurality of wordline groups, each wordline group of the plurality of wordline groups including a set of even wordlines and a set of odd wordlines, and control logic, operatively coupled with the memory array, to perform operations including identifying a set of failing wordline groups from the plurality of wordline groups, the set of failing wordline groups including at least one failing wordline group determined to have failed a first erase verify of an erase verify process, and causing a second erase verify of the erase verify process to be performed sequentially with respect to each failing wordline group of the set of failing wordline groups.