Sequestered Memory for Selective Cache Metadata Storage

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Solution Overview

Problem

The slow access times and high power consumption of storage subsystems, particularly in HDDs, are exacerbated by the need for mechanical movement of read/write heads, necessitating improved memory resource allocation for cached data.

Innovation Solution

A sequestered memory region is used to selectively store metadata corresponding to cached data, allowing for efficient storage and retrieval of metadata separately from the cache, with mechanisms to determine the conditions under which metadata is stored in the sequestered memory based on data characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If metadata is stored in the same cache memory as data, then memory utilization is improved, but access time increases and power consumption increases

Engineering Contradiction:
Improvememory utilizationVSAvoidaccess time
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The patent divides the cache memory into two separate regions: a data cache region for storing cached data and a metadata cache region for storing metadata. This segmentation allows independent access to data and metadata, improving access time while maintaining high memory utilization through specialized optimization of each region.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent extracts metadata from the data cache and stores it in a separate metadata cache region. This extraction eliminates the need to access mixed data-metadata structures, reducing access time overhead while the separate metadata cache maintains high utilization through dedicated metadata storage.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 3:

The patent introduces a new dimension to cache organization by creating a hierarchical structure with data cache at one level and metadata cache at another level. This dimensional separation enables parallel access paths, improving access time while maintaining utilization through coordinated management of both cache levels.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If metadata is stored in the same cache memory as data, then memory utilization is improved, but power consumption increases

Engineering Contradiction:
Improvememory utilizationVSAvoidpower consumption
Core Design Contradiction:
Quantity of substanceVSUse of energy by moving object

Solution Approach 1:

The patent segments cache memory into data cache and metadata cache regions, allowing the system to power down or put into low-power state only the data cache region when metadata access is not required, thereby reducing overall power consumption while maintaining memory utilization through the active metadata cache.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

By extracting metadata storage into a separate cache region, the patent enables independent power management where the metadata cache can remain active with low power consumption while the data cache enters low-power states, overall reducing system power consumption while maintaining high memory utilization.

Inventive Principle:
Principle #2Taking out (Extraction)

3Productivity

If cache memory is used to hold recent read/write results, then storage device performance is improved, but the storage device cannot remain in low power state

Engineering Contradiction:
Improvestorage device performanceVSAvoidlow power state duration
Core Design Contradiction:
ProductivityVSDuration of action of stationary object

Solution Approach 1:

The patent segments the cache system into data cache and metadata cache, enabling the storage device to maintain performance through the metadata cache while allowing the data cache to enter and remain in low-power states for longer durations, as metadata can be accessed independently to maintain operational performance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements periodic refresh or activation of the data cache from the metadata cache, allowing the storage device to remain in low-power state for extended periods while periodically activating data cache operations to maintain performance requirements, thus extending low-power state duration.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentEP4002131B1Sequestered memory for selective storage of metadata corresponding to cached data
Publication Date: 2025.10.08 INTEL CORP
  • EP4002131B1 patent drawingFigure 1
  • EP4002131B1 patent drawingFigure 2A
  • EP4002131B1 patent drawingFigure 2B

AI summary

Techniques and mechanisms for metadata, which corresponds to cached data, to be selectively stored to a sequestered memory region. In an embodiment, integrated circuitry evaluates whether a line of a cache can accommodate a first representation of both the data and some corresponding metadata. Where the cache line can accommodate the first representation, said first representation is generated and stored to the line. Otherwise, a second representation of the data is generated and stored to a cache line, and the metadata is stored to a sequestered memory region that is external to the cache. The cache line include an indication as to whether the metadata is represented in the cache line, or is stored in the sequestered memory region. In another embodiment, a metric of utilization of the sequestered memory region is provided to software which determines whether a capacity of the sequestered memory region is to be modified.