Programmable SerDes Bit Alignment at the Serial-to-Parallel Stage

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Conventional serial-to-parallel converters in high-speed communication systems require significant hardware for bit alignment and mapping, consuming power and chip area, which is inefficient.

Innovation Solution

A serial-to-parallel converter with multiple cascaded stages and demultiplexers, incorporating programmable demultiplexer control circuits and a pattern detector to enable clock signal generation and bit alignment, reducing the need for additional hardware by programmable mapping of serial to parallel data.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional serial-to-parallel converters use traditional bit alignment and mapping hardware, then bit alignment accuracy is improved, but device complexity and chip area increase

Engineering Contradiction:

Improvebit alignment accuracyVSAvoidhardware complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent changes the operational parameters of the demultiplexer by using programmable control circuits that can dynamically adjust the demultiplexer's behavior based on detected data patterns. This allows the system to achieve bit alignment through parameter adjustment rather than complex dedicated alignment hardware, thereby maintaining alignment accuracy while reducing device complexity

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The system performs self-alignment by detecting patterns in the incoming serial data stream and automatically adjusting its own demultiplexer control parameters. The converter essentially aligns itself without requiring external alignment hardware or complex internal alignment circuits, reducing overall device complexity while maintaining alignment precision

Inventive Principle:

Principle #25Self-service

2Measurement precision

If conventional serial-to-parallel converters include additional alignment components, then bit alignment capability is improved, but power consumption increases

Engineering Contradiction:

Improvebit alignment capabilityVSAvoidpower consumption

Core Design Contradiction:

Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The demultiplexer control circuits serve multiple functions: they control the normal demultiplexing operation, detect data patterns, and perform bit alignment based on detected patterns. By making the control circuits multi-functional, the patent eliminates the need for separate dedicated alignment components, thereby reducing power consumption while maintaining bit alignment capability

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the bit alignment function with the existing demultiplexer control circuits. Instead of having separate alignment hardware that would consume additional power, the alignment functionality is combined into the control circuits that already exist for demultiplexer operation, reducing overall power consumption while maintaining alignment capability

Inventive Principle:

Principle #5Merging (Combining)

3Measurement precision

If conventional serial-to-parallel converters use fixed mapping hardware, then mapping accuracy is improved, but adaptability decreases

Engineering Contradiction:

Improvemapping accuracyVSAvoidmapping adaptability

Core Design Contradiction:

Measurement precisionVSAdaptability or versatility

Solution Approach 1:

The patent transforms the static, fixed mapping hardware into a dynamic system where the demultiplexer control circuits can be programmably reconfigured based on detected data patterns. This allows the mapping behavior to adapt dynamically to different data formats and protocols while maintaining accurate mapping through programmable control, thus improving both adaptability and preserving mapping accuracy

Inventive Principle:

Principle #15Dynamics

4Device complexity

If conventional serial-to-parallel converters reduce hardware components, then device complexity is reduced, but bit alignment precision may deteriorate

Engineering Contradiction:

Improvehardware complexityVSAvoidbit alignment precision

Core Design Contradiction:

Device complexityVSMeasurement precision

Solution Approach 1:

The patent replaces the mechanical/physical alignment hardware with a software-based approach using programmable control circuits that detect patterns and dynamically adjust demultiplexer parameters. This substitution of physical alignment mechanisms with intelligent software control maintains bit alignment precision while significantly reducing hardware complexity

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS10536165B1Programmable bit alignment at serial-to-parallel stage of SerDes

Publication Date: 2020.01.14 QUALCOMM INC

AI summary

In certain aspects, a serial-to-parallel converter includes multiple cascaded stages configured to convert a serial data stream into multiple parallel data signals, wherein each of the stages includes one or more demultiplexers. The serial-to-parallel converter also includes demultiplexer control circuits, wherein each of the demultiplexer control circuits is coupled to the one or more demultiplexers of a respective one of the stages, and a pattern detector coupled to the demultiplexer control circuits.