SerDes Clock Data Recovery Broadcast Power Reduction
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Solution Overview
Problem
Conventional SerDes interfaces experience high power consumption due to individual clock data recovery (CDR) operations in each lane, which multiplies power usage with the number of lanes, necessitating a more power-efficient CDR scheme.
Innovation Solution
Implementing a master lane with a CDR module to generate and broadcast master data sample clock control signals to slave lanes, allowing slave lanes to power down their local CDR modules during low power mode and use the master signals, and periodically rotating lanes to act as master for accurate clock signal generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each lane performs individual CDR operations to ensure accurate clock recovery, then clock recovery accuracy is maintained, but power consumption increases proportionally with the number of lanes
Solution Approach 1:
The system segments CDR operations into master lane (performs full CDR) and slave lanes (use broadcast signals), dividing the power consumption burden while maintaining overall clock recovery accuracy across all lanes
Solution Approach 2:
Multiple slave lanes merge their clock recovery function by using the master lane's broadcast CDR signals instead of performing individual CDR operations, consolidating power consumption into a single master lane while maintaining synchronized operation across all lanes
2Use of energy by moving object
If slave lanes power down their local CDR modules to reduce power consumption, then power efficiency improves, but dependency on master lane increases and may affect reliability
Solution Approach 1:
The master lane acts as an intermediary that performs CDR operations and broadcasts the recovered clock signals to all slave lanes, enabling slave lanes to power down their local CDR modules while maintaining reliable clock recovery through the master lane's intermediary function
3Use of energy by moving object
If a single master lane performs CDR for all slave lanes to minimize power consumption, then power consumption is reduced, but the master lane becomes a single point of failure
Solution Approach 1:
The system dynamically switches between different operational modes (single master, multiple masters, round-robin rotation) based on system conditions and requirements, allowing the master lane configuration to adapt and change rather than remaining static, thereby improving fault tolerance while maintaining power efficiency
Data Source
AI summary
Clock data recovery broadcast for multi-lane SerDes is disclosed. In some implementations, a serial input/output (I/O) interface includes a master lane and a plurality of slave lanes to receive serial incoming data. The master lane has a master clock and data recovery (CDR) module to generate master data sample clock control signals. The master data sample clock control signals can be broadcasted to the slave lanes. Furthermore, each of the plurality of slave lanes having a slave CDR module. The slave CDR module can include a clock edge tracking module to generate local data sample clock control signals, and a multiplexer to select the master data sample clock control signals or local data sample clock control signals to apply in the respective slave lane in response to a signal from a CDR controller indicative of a low power mode.