SerDes Receiver CDR Pulse Shaping With Decoupled DFFE Equalization
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Solution Overview
Problem
Traditional SerDes architectures face limitations in coupling between clock data recovery (CDR) and equalization adaptation, leading to sub-optimal CDR locking points and sensitivity to transmitter settings, with DFE being limited to postcursor ISI correction and prone to noise amplification by FFE.
Innovation Solution
A SerDes receiver architecture incorporating a Decision Feedforward Equalizer (DFFE) for both precursor and postcursor ISI correction, decoupling CDR and equalization adaptations, and using a multi-tap DFFE topology to achieve symmetric pulse responses and robust performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Feedforward Equalizer (FFE) is used to correct both precursor and postcursor ISI, then ISI correction capability is improved, but noise and crosstalk are amplified
Solution Approach 1:
The equalization function is segmented into two distinct components: FFE for precursor ISI correction and DFE for postcursor ISI correction. This segmentation allows each equalizer type to operate in its optimal regime, with FFE handling precursor interference without excessive noise amplification and DFE handling postcursor interference without error propagation issues.
Solution Approach 2:
The patent applies partial action by using multiple FFE taps for precursor ISI correction followed by one or two DFE taps for postcursor correction. This partial application of each equalizer type optimizes performance by applying just enough correction from each source without over-correcting and introducing harmful side effects.
2Object-affected harmful factors
If Decision Feedback Equalizer (DFE) is used to correct postcursor ISI, then noise amplification is avoided, but precursor ISI correction capability is lost
Solution Approach 1:
The equalization function is segmented into two distinct components: FFE for precursor ISI correction and DFE for postcursor ISI correction. This segmentation allows each equalizer type to operate in its optimal regime, with FFE handling precursor interference without excessive noise amplification and DFE handling postcursor interference without error propagation issues.
3Reliability
If multiple taps of FFE are used for both precursor and postcursor ISI correction, then ISI correction is improved, but device complexity increases
Solution Approach 1:
The patent applies partial action by using multiple FFE taps for precursor ISI correction followed by one or two DFE taps for postcursor correction. This partial application of each equalizer type optimizes performance by applying just enough correction from each source without over-correcting and introducing harmful side effects.
4Device complexity
If CDR and equalization adaptations are coupled, then system integration is improved, but CDR locking point stability deteriorates
Solution Approach 1:
The patent segments the adaptation processes by providing separate adaptation paths: one for equalization (optimizing FFE and DFE coefficients) and another for CDR (optimizing clock recovery). This segmentation decouples the two adaptation processes, allowing them to converge independently to their respective optimal points without interfering with each other's stability.
Data Source
AI summary
An optimized pulse shaping clock data recovery system is provided that includes a slicer configured to receive a signal and provide an initial set of tentative decisions to a decision feedforward equalizer, where the decision feedforward equalizer provides a fully equalized output signal. The slicer may be incorporated as part of decision feedback equalizer to provide better quality tentative decisions. The clock data recovery system also receives the first output signal that is partially equalized in such a way as to optimally shape it for a clock to sample it at an ideal location by providing an adjustment signal to the analog to digital controller.