SERDES CDR Lock Time Measurement Without Clock Frequency Reduction
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Solution Overview
Problem
Existing methods for determining the lock time of a clock and data recovery (CDR) circuit in high-speed data communication systems are inaccurate and complex, particularly in point-to-multipoint communication networks like passive optical networks, where synchronizing the clock signal with upstream signals is crucial to prevent data corruption.
Innovation Solution
A lock time measurement system that utilizes a serializer-deserializer (SERDES), a phase locked loop (PLL), and a multiplexer to measure the lock time without reducing the frequency of the recovered clock signal, using existing transmitter components and avoiding additional complex circuits, thereby maintaining accuracy and reducing system complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the frequency of the recovered clock signal is reduced using decoders to determine lock time, then the measurement process becomes simpler, but the accuracy of lock time measurement deteriorates
Solution Approach 1:
The patent extracts only the necessary timing information from the high-frequency clock signal without reducing its frequency. A timing capture circuit selectively captures lock time information directly from the original high-frequency clock signal, eliminating the need for frequency reduction while maintaining measurement accuracy.
Solution Approach 2:
The patent creates a copy of the timing information from the high-frequency clock signal using a timing capture circuit. This copy contains the lock time measurement data without requiring modification of the original clock signal frequency, thus preserving accuracy while simplifying the measurement process.
2Measurement precision
If additional circuits such as a clock driver block are implemented to determine lock time, then the measurement capability is improved, but the system complexity and area increase
Solution Approach 1:
The patent merges the lock time measurement function with the existing clock and data recovery circuit by integrating a timing capture circuit that utilizes the recovered clock signal directly. This integration eliminates the need for separate additional circuits like clock driver blocks, reducing overall system complexity and area while maintaining measurement capability.
Solution Approach 2:
The timing capture circuit serves multiple functions: it captures the lock time measurement data from the recovered clock signal and can operate with the existing CDR circuit architecture. This multi-functional approach improves measurement capability without requiring dedicated additional circuits, thereby reducing system complexity.
3Productivity
If the CDR circuit synchronizes phase in a short period for burst mode upstream signals, then data transmission efficiency is improved, but the difficulty of determining accurate lock time increases
Solution Approach 1:
The timing capture circuit is pre-configured to capture lock time information at the appropriate moment during the phase synchronization process. By preparing the capture mechanism in advance and triggering it when phase locking occurs, the system can determine accurate lock time even during rapid burst mode synchronization, maintaining both transmission efficiency and measurement accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system accurately measures lock time without reducing clock signal frequency, maintaining high accuracy and reducing system complexity, making it more efficient and cost-effective compared to prior art solutions.
Implementation Method 1
A CDR circuit generates a clock signal that is frequency and phase synchronized with the data received from the transmitter
Data Source
AI summary
A lock time measurement system to determine a lock time includes a measurement device, a serializer-deserializer (SERDES), a pattern generator, and a splitter. In a first mode, the SERDES receives first data from the pattern generator by way of the splitter. A receiver of the SERDES outputs a recovered clock signal based on the first data to a transmitter. The transmitter includes a serializer and a multiplexer. The serializer receives the recovered clock signal by way of the multiplexer and modifies second data based on the recovered clock signal and outputs serial data. A measurement device, connected to the transmitter and the splitter determines the lock time. In a second mode, the SERDES functions as a transmitter for transmitting data and a receiver for receiving data in a communication link. The system has a better accuracy and utilizes existing receiver and driver circuits.