SerDes Receiver CDR Pulse Shaping with Decoupled ISI Equalization
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Solution Overview
Problem
Traditional SerDes architectures face limitations in coupling between clock data recovery (CDR) and equalization adaptation, leading to sub-optimal CDR locking points and sensitivity to transmitter settings, with FFE dominant architectures being noise-sensitive due to limited postcursor ISI correction and error propagation in DFE.
Innovation Solution
A SerDes receiver architecture integrating a Decision Feedforward Equalizer (DFFE) for both precursor and postcursor ISI correction, decoupling CDR and equalization adaptations, and using a multi-tap DFFE topology to achieve symmetric pulse responses and robust performance across a wide range of transmitter settings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FFE is used for ISI correction, then both precursor and postcursor ISI can be corrected, but noise and crosstalk are amplified
Solution Approach 1:
The equalization function is segmented into two distinct components: FFE for precursor ISI correction and DFE for postcursor ISI correction. This segmentation allows each equalizer type to operate in its optimal regime, with FFE handling precursor interference without excessive noise amplification and DFE handling postcursor interference without error propagation
Solution Approach 2:
The patent combines FFE and DFE into a hybrid equalization architecture where both equalizers work together in sequence. The FFE output feeds into the DFE, creating a unified equalization system that leverages the strengths of both approaches while mitigating their individual weaknesses
2Object-affected harmful factors
If DFE is used for postcursor ISI correction, then noise is not amplified, but error propagation occurs and it cannot correct precursor ISI
Solution Approach 1:
The equalization task is divided between FFE and DFE, with DFE specifically assigned to postcursor ISI correction where it excels at noise preservation. The segmentation ensures DFE operates only in its strength zone without attempting precursor correction
Solution Approach 2:
The DFE uses feedback from previously decided symbols to cancel postcursor ISI. The feedback mechanism allows DFE to use past decision information to improve current symbol detection without amplifying noise, while the hybrid architecture with FFE prevents error propagation by providing a clean reference signal
3Reliability
If multiple taps of FFE are used for ISI correction, then both precursor and postcursor ISI are corrected, but complexity increases and noise is boosted
Solution Approach 1:
The multi-tap equalization is segmented into FFE taps for precursor correction and DFE taps for postcursor correction. This segmentation reduces the total number of FFE taps needed, thereby reducing complexity and noise amplification while maintaining comprehensive ISI correction capability
Solution Approach 2:
Instead of using many FFE taps for all ISI correction, the patent uses a limited number of FFE taps for precursor correction and relies on DFE for postcursor correction. This partial action approach optimizes the balance between complexity and performance
4Adaptability or versatility
If CDR and equalization are coupled, then joint adaptation is achieved, but CDR locking point becomes sub-optimal and sensitive to transmitter settings
Solution Approach 1:
The adaptation process is segmented into equalization adaptation and CDR adaptation that operate independently. The equalization adapts FFE and DFE coefficients to minimize ISI, while CDR adapts the clock recovery separately. This segmentation decouples the two adaptation processes, allowing CDR to achieve optimal locking points independent of transmitter settings
Data Source
AI summary
An optimized pulse shaping clock data recovery system is provided that includes a slicer configured to receive a signal and provide an initial set of tentative decisions to a decision feedforward equalizer, where the decision feedforward equalizer provides a fully equalized output signal. The slicer may be incorporated as part of decision feedback equalizer to provide better quality tentative decisions. The clock data recovery system also receives the first output signal that is partially equalized in such a way as to optimally shape it for a clock to sample it at an ideal location by providing an adjustment signal to the analog to digital controller.