SERDES Clock Recovery with Eye Margin Measurement
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Solution Overview
Problem
Conventional clock and data recovery circuits lack the ability to determine whether the recovered clock is truly optimum and do not measure the operational margin along temporal and voltage directions, which is essential for ensuring effective data transfer in high-speed serial data transmission between LSIs.
Innovation Solution
A clock and data recovery circuit comprising a data sampling circuit, phase comparator, phase controller, phase interpolator, and control circuit that allows for the measurement of operational margin by varying the phase of the clock signal and threshold level, and plotting an eye pattern to represent the operational margin along both temporal and voltage directions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional clock and data recovery circuits are used, then data transfer is performed, but the operational margin cannot be measured along temporal and voltage directions
Solution Approach 1:
The invention divides the measurement function into separate controllable components: phase control for temporal direction and threshold control for voltage direction. This allows independent adjustment and measurement of operational margin in each direction without requiring complete circuit redesign.
Solution Approach 2:
The invention changes the parameters of existing circuit components by making the phase and threshold externally controllable. This enables the measurement of operational margin by varying these parameters systematically while monitoring data sampling accuracy.
2Adaptability or versatility
If the phase and threshold are fixed in conventional circuits, then the circuit operation is simple, but the operational margin cannot be adjusted or measured
Solution Approach 1:
The invention makes the phase interpolator and data sampling circuit multi-functional by enabling external control of phase and threshold parameters. These components can operate in both fixed-mode (normal operation) and adjustable-mode (measurement and optimization), serving multiple purposes without requiring separate dedicated circuits.
Data Source
AI summary
Disclosed is a clock-and-data recover circuit in which a data sampling circuit, a phase comparator, a phase controller and a phase interpolator make up a loop. The data sampling circuit samples serial input data, and the phase comparator receives an output from the data sampling circuit to detect the phase relationship between clock and the data. The phase controller outputs a phase control signal based on the result of phase comparison of the phase comparator to output a phase control signal. The phase interpolator receives a multi-phase clock composed of plural clock signals with different phases and supplies a clock signal having the phase interpolated based on the phase control signal, to the data sampling circuit. The clock and data recovery circuit further includes a second phase interpolator and a second data sampling circuit. The phase controller generates and outputs a second phase control signal to the second phase interpolator. The second phase interpolator receives the multi-phase clock and outputs a second clock signal having the phase interpolated based on the second phase control signal and supplies the second clock signal to the second data sampling circuit. The second data sampling circuit samples the input data based on the second clock signal from the second phase interpolator. Preferably, the second phase interpolator has a variably set threshold level for sampling the data.