SerDes Clock Interference Cancellation Using Mixed-Domain Calibration
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Solution Overview
Problem
High-density switch chips with SerDes lanes operating at different frequencies face significant interference issues due to clock signal coupling, degrading signal-to-noise ratio and bit error rate, which are difficult to predict and mitigate with traditional analog design and simulation tools.
Innovation Solution
A mixed-domain interference cancellation apparatus using a digital-interference-cancellation (DIC) circuit and an analog-interference-cancellation (AIC) circuit to detect and generate a cancellation signal, operating in both digital and analog domains to minimize clock-to-signal interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If multiple SerDes lanes share a single PLL with phase interpolator to conserve power and chip area, then power consumption and chip area are reduced, but clock signal coupling interference increases
Solution Approach 1:
The patent extracts the harmful clock signal from the mixed signal by using a band-pass filter tuned to the clock frequency to isolate and remove the clock coupling component, leaving the desired data signal intact
Solution Approach 2:
The patent converts the harmful clock coupling interference into a useful synchronization reference by using the filtered clock signal to control the phase interpolator, thereby eliminating interference while maintaining frequency alignment between Tx and Rx
2Reliability
If phase interpolator adjusts frequency offsets between Tx and Rx to enable synchronous operation, then synchronous operation is achieved, but unwanted tones at offset frequency appear in signal path
Solution Approach 1:
The patent introduces an intermediary band-pass filter between the mixed signal source and the phase interpolator to selectively pass the clock frequency while blocking other frequencies, thereby eliminating unwanted tones while maintaining synchronization
3Object-affected harmful factors
If traditional analog design and layout techniques are used to mitigate clock-to-signal interference, then some interference reduction is achieved, but fundamental physical limits and modeling accuracy prevent full prediction and counteraction
Solution Approach 1:
The patent employs feedback by continuously monitoring the mixed signal, filtering out the clock component, and using the cleaned signal to control the phase interpolator, thereby dynamically adapting to and eliminating interference that cannot be predicted by static modeling
Data Source
AI summary
An apparatus for canceling clock-to-signal interference in a multi-lane SerDes comprising an analog front-end circuit receiving an input signal from a signal path mixed with interference from a clock path. The apparatus includes a phase interpolator circuit implemented in the clock path to generate multiple phases of a clock signal and to provide a timing rotated by the phases for a track-and-hold circuit to sample the input signal and the interference in every cycle. The apparatus also includes an analog-to-digital converter configured to digitize the input signal and the interference to provide an ADC output and a digital-interference-cancellation circuit configured to demultiplex the ADC output and detect a baseline offset associated with the interference sampled at one of the phases in each demultiplexed path using a digital loop to calibrate the baseline offset.