SERDES Clock Path Mismatch Calibration
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Solution Overview
Problem
Effective clock path mismatches between data slicers and error slicers in receiver circuits, such as SERDES, lead to inaccurate bit determination and reduced link margin due to manufacturing variations and design limitations, especially at high data speeds.
Innovation Solution
A calibration subsystem iteratively shifts and compares sampling of data and error slicer decisions across multiple clock locations to determine an effective clock mismatch window, applying a clocking offset to either the data or error slicer to compensate for these mismatches, thereby aligning their sampling times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If data slicers and error slicers are implemented with separate clock paths in receiver circuits, then each slicer can be independently optimized for its function, but manufacturing variations cause clock path delays to differ, leading to effective clock path mismatches that reduce bit determination accuracy and link margin
Solution Approach 1:
The patent applies preliminary action by performing calibration of clock path delays before normal operation. The system measures the clock path delay difference between data slicer and error slicer during a calibration phase, then applies compensation delays to align the sampling clocks. This preliminary calibration ensures that subsequent bit determination operations occur with synchronized timing, eliminating the accuracy problems caused by manufacturing variations in separate clock paths
Solution Approach 2:
The patent changes the timing parameters of the clock paths by introducing adjustable delay elements in the clock paths of either the data slicer or error slicer. During calibration, the delay values are measured and then adjusted to compensate for manufacturing variations. This parameter adjustment allows the system to maintain synchronized sampling despite using separate clock paths for independent optimization
2Ease of manufacture
If separate clock paths are used for data slicer and error slicer, then design flexibility is improved, but clock path delay differences cause sampling timing misalignment that reduces link margin
Solution Approach 1:
The calibration process performs preliminary measurement and compensation of clock path delays before the receiver operates in its normal high-speed mode. By measuring the delay difference between separate clock paths during manufacturing or initial setup, and pre-adjusting the delays to match, the system maintains reliable operation with adequate link margin while preserving the design flexibility of separate clock paths
Solution Approach 2:
The system uses feedback from the calibration process to adjust clock path delays. The calibration measures the actual delay difference and feeds this information back to the delay adjustment mechanisms, which then compensate for the mismatch. This feedback loop ensures that even with manufacturing variations affecting separate clock paths, the sampling timing remains aligned and link margin is maintained
3Ease of operation
If clock paths are synchronized without calibration, then operation is simpler, but manufacturing variations cause effective clock path mismatches that frustrate accurate determination of serial bits
Solution Approach 1:
The system performs self-calibration by automatically measuring its own clock path delay differences and adjusting its own delay elements without external intervention. The calibration process is integrated into the receiver operation, allowing the system to self-correct for manufacturing variations in clock paths, thereby maintaining bit determination accuracy while keeping the operation simple and automated
Data Source
AI summary
Embodiments include systems and methods for calibrating effective clock path mismatches in a receiver circuit. For example, a serializer/deserializer (SERDES) circuit includes a data slicer that generates data sampler decisions by sampling an input signal according to a clocking signal, and an error slicer that generates error slicer samples by sampling the input signal according to the clocking signal. Each of the data slicer and error slicer has an associated clock path delay, and the delays are typically different (e.g., due to manufacturing differences). A calibrator performs iteratively shifted sampling and comparing of the data sampler decisions and the error slicer samples over a plurality of clocking locations to determine an effective clock path mismatch. The calibrator can then determine and apply a clocking offset to the data slicer and/or the error slicer to effectively shift data and error sampling, thereby compensating for the effective clock path mismatch.