Two-Wire SerDes Clock Multiplexing for Area and Power Reduction
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Solution Overview
Problem
The implementation of multiple high-speed clock frequencies in communication networks using distinct busses increases spatial area and power consumption, as each bus requires isolation and additional resources, complicating IC designs.
Innovation Solution
A two wire-based clock multiplication unit (CMU) that encodes high-speed clock frequencies in differential and common modes, allowing simultaneous transmission on a single pair of wires, reducing the need for physical isolation and resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If distinct busses are used for different high-speed clock frequencies, then clock frequency transmission is achieved, but spatial area and power consumption increase
Solution Approach 1:
The patent combines multiple high-speed clock frequency transmissions onto a single shared bus infrastructure rather than using separate distinct busses for each frequency. The summer circuit merges the differential mode clock signal and common mode clock signal onto the same physical bus, thereby reducing spatial area requirements while maintaining the ability to transmit multiple clock frequencies simultaneously
Solution Approach 2:
The shared bus is designed to serve multiple functions by carrying both differential mode encoded clock frequencies and common mode encoded clock frequencies. This universal bus structure eliminates the need for frequency-specific dedicated busses, reducing overall spatial area while maintaining full functionality for multiple clock rate transmissions
2Speed
If distinct busses are used for different high-speed clock frequencies, then clock frequency transmission is achieved, but power consumption increases
Solution Approach 1:
By merging multiple clock frequency transmissions onto a single shared bus, the patent reduces the total number of conductors that require power for signal transmission. The summer circuit combines signals so that multiple clock frequencies share the same physical transmission medium, thereby reducing overall power consumption compared to having separate powered busses for each frequency
Solution Approach 2:
The shared bus performs multiple transmission functions simultaneously, carrying both differential mode and common mode encoded clock signals. This multi-functional approach eliminates redundant power consumption that would occur with separate dedicated busses, as the single bus infrastructure supports all clock frequency transmission needs
3Reliability
If multiple distinct busses are arranged with isolation, then clock frequency transmission reliability is improved, but spatial area costs increase
Solution Approach 1:
The patent changes the encoding parameters of clock signals by using two different encoding schemes: differential mode encoding for one clock frequency and common mode encoding for another. This parameter change allows both signals to coexist on the same bus without requiring physical isolation, maintaining transmission reliability while reducing spatial area requirements
4Area of stationary object
If differential mode and common mode encoding are used simultaneously, then multiple clock frequencies are transmitted on two wires, but signal separation complexity increases
Solution Approach 1:
The patent uses parameter changes in signal encoding (differential mode vs. common mode) to enable frequency multiplexing on a shared bus. The summer circuit exploits these parameter differences to separate and process the different clock frequencies, managing signal separation complexity through parameter-based discrimination rather than requiring complex spatial or temporal separation mechanisms
Data Source
AI summary
The disclosed systems, structures, and methods are directed to a two wire-based clock multiplication unit (CMU), employing a first phase lock loop (PLL) configured to generate a first high-speed clock frequency f1 encoded in differential mode, a second PLL configured to generate a second high-speed clock frequency f2 encoded in common mode, and a summer configured to combine the differential mode encoding the first high-speed clock frequency f1 and the common mode encoding the second high-speed clock frequency f2 and transmit the combined differential and common mode high-speed clock frequencies on a two wire-based conductor bus. In addition, systems, structures, and methods directed to a two wire-based clock recovery module and a two wire-based clock recovery module have also been disclosed.