Two-Wire SerDes Clock Multiplexing for Multi-Rate Distribution
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Solution Overview
Problem
Existing IC designs incorporating multiple serializer/deserializer (SerDes) macros face challenges with increased spatial area and power consumption due to the need for multiple busses to accommodate varying high-speed clock frequencies, which are required to handle different data rates in communication networks.
Innovation Solution
A two wire-based clock multiplication unit (CMU) that combines differential and common mode high-speed clock frequencies for transmission, using a phase lock loop (PLL) to generate these frequencies and a summer to combine them on a two wire-based conductor bus, along with a clock recovery module to separate and amplify these frequencies as needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple distinct busses are used to transmit different high-speed clock frequencies to various SerDess, then the ability to accommodate varying data rates is improved, but the spatial area required increases
Solution Approach 1:
The patent combines multiple clock frequency transmissions into a single shared bus by using different modulation schemes (differential mode for first clock frequency, common mode for second clock frequency) on the same physical conductor, thereby reducing spatial area while maintaining adaptability to various data rates
Solution Approach 2:
The shared bus is designed to perform multiple functions by transmitting different clock frequencies through the same conduit using mode differentiation, allowing a single bus structure to serve multiple SerDess with varying data rate requirements
2Adaptability or versatility
If multiple distinct busses are used to transmit different high-speed clock frequencies, then different clock rates can be supplied to various SerDess, but the power consumption increases
Solution Approach 1:
Multiple clock frequency transmissions are merged into a single shared bus, reducing the total number of conductors and associated power consumption while maintaining the capability to supply different clock rates to various SerDess through mode-based differentiation
3Adaptability or versatility
If multiple distinct busses are implemented for different high-speed clock frequencies, then clock frequency distribution to various SerDess is enabled, but the device complexity increases
Solution Approach 1:
The patent merges multiple clock distribution functions into a single shared bus structure, using modulation mode (differential vs. common) to differentiate between clock frequencies, thereby reducing device complexity while maintaining full distribution capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces spatial area and power consumption by utilizing only two wires for multiple clock frequencies, enabling efficient operation within IC design constraints while maintaining effective clock frequency distribution.
Implementation Method 1
a first phase lock loop (PLL) configured to generate a first high-speed clock frequency f1
Implementation Method 2
a first high-speed clock frequency f1 encoded in differential mode, a second PLL configured to generate a second high-speed clock frequency f2 encoded in common mode and a summer configured to combine the differential mode encoding the first high-speed clock frequency f1 and the common mode encoding the second high-speed clock frequency f2
Data Source
Figure 1~2
Figure 3
Figure 4
AI summary
The disclosed systems, structures, and methods are directed to a two wire-based clock multiplication unit (CMU), employing a first phase lock loop (PLL) configured to generate a first high-speed clock frequency f 1 encoded in differential mode, a second PLL configured to generate a second high-speed clock frequency f 2 encoded in common mode, and a summer configured to combine the differential mode encoding the first high-speed clock frequency f 1 and the common mode encoding the second high-speed clock frequency f 2 and transmit the combined differential and common mode high-speed clock frequencies on a two wire-based conductor bus. In addition, systems, structures, and methods directed to a two wire-based clock recovery module and a two wire-based clock recovery module have also been disclosed.