SERDES Clock Timing Control for Stable I/Q Phase Alignment
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Solution Overview
Problem
High-speed SERDES systems face challenges in maintaining the correct timing relationship between in-phase and quadrature clock signals due to variations in frequency division results based on the reset state and relationships between these signal groups, leading to disorders in timing circuits.
Innovation Solution
A timing control device and method utilizing independent sampling and clock gating techniques to ensure a correct sequence of in-phase/orthogonal signal groups, employing a sampling circuit with multiple samplers and a gating circuit with switch circuits to manage clock signals with specific phase differences and trigger points, ensuring absolute timing relationships.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If an independent frequency divider is used to separately divide in-phase/quadrature clock signals, then independent timing control of individual signals is achieved, but frequency division results yield several different results based on reset state and signal relationships causing timing disorders
Solution Approach 1:
The patent divides the frequency division process into two independent stages: first dividing the reference clock to generate intermediate clock signals, then dividing those intermediate signals to generate final in-phase and quadrature clock signals. This segmentation isolates the reset state influence to only the first division stage, ensuring the second stage always produces consistent 90-degree phase difference results regardless of reset conditions.
Solution Approach 2:
The patent performs preliminary frequency division to generate intermediate clock signals before the final division stage. By establishing a stable intermediate clock signal first, the system prepares a controlled baseline that ensures subsequent division operations produce predictable and consistent phase relationships, preventing timing disorders caused by varying reset states.
2Adaptability or versatility
If the reset signal trigger point varies relative to clock signal edges, then different frequency division results occur, but this causes disorders in timing circuits
Solution Approach 1:
The patent segments the frequency division into two independent stages, isolating the reset signal's variable trigger point influence to only the first division stage. The second division stage operates independently on intermediate clock signals, ensuring consistent phase relationships regardless of when the reset signal triggers relative to clock edges.
Solution Approach 2:
The patent introduces intermediate clock signals as a mediator between the reference clock and final in-phase/quadrature outputs. These intermediate signals act as a buffer that absorbs the variability from reset timing, translating inconsistent reset triggers into consistent intermediate signals that then produce stable final outputs.
3Ease of operation
If in-phase/quadrature clock signals appear sequentially after reset trigger, then in-phase leads quadrature by 90 degrees, but if reset trigger appears between edges, quadrature leads in-phase causing phase relationship disorders
Solution Approach 1:
The patent divides the clock signal generation into two independent division stages, separating the influence of reset timing on phase relationships. The first stage generates intermediate signals that are then divided in the second stage to produce final in-phase and quadrature signals with consistent 90-degree phase difference, regardless of reset trigger positioning.
Solution Approach 2:
The patent uses the same division logic and circuit structure for both in-phase and quadrature signal generation, copying the division process while maintaining consistent phase relationships. This symmetric approach ensures that regardless of reset timing, both signals undergo identical processing that preserves the 90-degree phase difference.
Data Source
AI summary
A timing control device and a timing control method for a high frequency signal system, the timing control method respectively control trigger points of reset signals, and process the controlled reset signals and clock signals to obtain a signal group with having an absolute timing relationship.