SERDES Clock Phase Locking Across Cores and Boards
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Solution Overview
Problem
High-speed serializer/deserializer (SERDES) devices face challenges in synchronizing transmitter clock signals with receiver clock signals across different SERDES cores, substrates, or boards, leading to frequency drift issues that compromise data integrity, especially at higher speeds like 4 Gigahertz or more.
Innovation Solution
A transceiver system with phase-locked SERDES cores that transfer receive clock phase data to synchronize the transmit clock signal with the receive clock signal, using a method that adjusts the transmit clock phase based on the receive clock phase difference and direction, ensuring data integrity across different components and substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a common clock is used at the receiver and transmitter, then clock matching is improved, but device complexity and feasibility deteriorate due to the large distance between components and the impracticality of running high-frequency lines
Solution Approach 1:
The patent introduces an intermediary mechanism where the receiver extracts clock information from incoming data and transfers it to the transmitter, which then uses this information to synchronize its clock. This mediator approach avoids the need for direct common clock connections between distant components.
Solution Approach 2:
The patent replaces the mechanical/electrical connection of common clock lines with a signal processing approach. The clock synchronization is achieved through digital signal processing and phase adjustment algorithms rather than physical clock distribution networks.
2Stability of the object's composition
If direct clock-matching is maintained over distance, then frequency stability is improved, but feasibility deteriorates due to the relatively large distance between components
Solution Approach 1:
The patent implements a feedback mechanism where the receiver continuously monitors the incoming signal characteristics, extracts clock phase information, and sends this information back to the transmitter. The transmitter then adjusts its clock phase based on this feedback to maintain synchronization despite distance variations.
Solution Approach 2:
The patent makes the clock phase dynamic and adjustable rather than fixed. The transmitter clock phase can be dynamically adjusted based on the received clock information to compensate for distance-induced frequency drift, enabling adaptation to varying transmission conditions.
3Productivity
If frequency changes are allowed to track data frequency, then productivity is improved, but reliability deteriorates due to potential violation of minimum pulse width requirements
Solution Approach 1:
The patent performs preliminary action by adjusting the clock phase before data transfer issues arise. The system continuously monitors and adjusts the clock phase in advance, preventing frequency drift from reaching levels that would violate pulse width requirements or cause data integrity problems.
Solution Approach 2:
The patent uses feedback control to continuously monitor the relationship between transmit and receive clock phases and make real-time adjustments. This feedback mechanism ensures that frequency changes remain within safe boundaries that maintain minimum pulse width requirements while still allowing high-speed data transfer.
Data Source
AI summary
A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed.