SerDes Interface Clock Conversion for Mixed Data Rate Transfer
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Solution Overview
Problem
Conventional SerDes interfaces are limited in their ability to handle data transmission at different communication rates, making it difficult to use the same SerDes for devices with varying specifications, such as 16-bit parallel data at 180 MHz and 1-bit signals at 160 MHz, without compromising communication efficiency.
Innovation Solution
A SerDes interface circuit incorporating a FIFO, flip-flop, and output state machine that inputs and processes data at different clock frequencies to generate parallel data with consecutive same bits, allowing for data transmission at various communication rates using the same SerDes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the same SerDes is used for devices with different communication rates, then device compatibility and integration are improved, but communication reliability and data transmission accuracy deteriorate due to frequency conversion requirements
Solution Approach 1:
The patent introduces a frequency conversion circuit as an intermediary component between the SerDes and data sources with different communication rates. This mediator performs frequency conversion to match the SerDes operating rate, enabling the same SerDes to communicate with devices at different rates while maintaining communication reliability through proper frequency matching
2Adaptability or versatility
If frequency conversion is implemented to handle different communication rates, then adaptability to various devices is improved, but circuit complexity increases due to additional conversion components
Solution Approach 1:
The patent segments the frequency conversion function into separate, modular components including a frequency conversion circuit and a selection circuit. This segmentation allows the system to handle different communication rates through modular addition rather than requiring a completely complex reconfiguration, reducing overall circuit complexity while maintaining adaptability
3Reliability
If multiple SerDes interfaces are used for different communication rates, then communication reliability for each rate is ensured, but device complexity and integration difficulty increase
Solution Approach 1:
The patent implements a universal SerDes interface that can handle multiple communication rates through frequency conversion. The same SerDes is configured to work with different data sources (16-bit parallel data at 180MHz, 1-bit signal at 160MHz, etc.) by dynamically adjusting the frequency conversion ratio, eliminating the need for multiple dedicated SerDes interfaces while maintaining communication reliability
Data Source
AI summary
The present invention provides a SerDes interface circuit and a control device which make it possible to use the same SerDes to perform data transfer of different communication rates. The present invention includes: a FIFO that inputs a first clock of a first frequency, first transmission data based on the first clock, and a second clock of a second frequency which is different from the first frequency, and that outputs the first transmission data on the basis of the second clock in the order of input; a flipflop that fetches and holds the FIFO output on the basis of the second clock; and an output state machine operating with the second clock that inputs the FIFO output and the flipflop output, and generates parallel data in which the same data corresponding to the first transmission data is consecutive.