Compressed SerDes Clock Scaling for Faster FPGA Prototyping
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Solution Overview
Problem
The existing methods for testing and validating integrated circuit designs using Field Programmable Gate Array (FPGA) prototyping systems face significant challenges due to the long test runtime, which is directly related to the clock period and the delay caused by serializer-deserializer (SerDes) components, especially when dealing with multiple FPGA chips.
Innovation Solution
The proposed solution involves dynamic clock scaling and data compression, where the clock period is adjusted based on the compression ratio, and data is compressed before serialization to reduce the number of bits sent through SerDes, thereby minimizing delay and test runtime. This is achieved through a method that includes a compression block, decision block, multiplexer, serializer, clock generator, deserializer, and demultiplexer, which dynamically configure the multiplexing and demultiplexing factors based on the compression ratio to select appropriate clock signals and reduce the overall test runtime.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If data is transmitted without compression through SerDes components, then data transfer is simple and direct, but test runtime is significantly extended due to SerDes delay
Solution Approach 1:
The patent applies preliminary action by compressing the data before it enters the SerDes transmission path. The compression block processes the input data in advance, reducing its size before serialization, which directly reduces the transmission time through the SerDes components and thereby decreases the overall test runtime.
Solution Approach 2:
The compression block acts as an intermediary component between the data source and the SerDes transmission path. It mediates the data flow by transforming the original data into a compressed form, which then passes through the SerDes components, effectively reducing the bottleneck caused by SerDes delay without requiring changes to the SerDes infrastructure itself.
2Loss of time
If clock period is kept fixed for sampling data, then timing is simple and stable, but test runtime is extended due to SerDes delay
Solution Approach 1:
The patent applies dynamics by making the clock period variable rather than fixed. The clock generation block dynamically adjusts the clock period based on the compression ratio, creating a scaled clock signal that adapts to the compressed data rate. This dynamic clock scaling allows the system to optimize test runtime by matching the clock frequency to the actual data transmission rate after compression.
Solution Approach 2:
The patent changes the time parameter of the clock signal by scaling the clock period according to the compression ratio. The formula clock_period_scaled = clock_period_original × compression_ratio demonstrates this parameter change, where the clock period is adjusted proportionally to the compression achieved, thereby synchronizing the sampling rate with the reduced data rate and reducing overall test runtime.
3Productivity
If data is compressed before serialization, then transmission time is reduced, but device complexity increases due to compression and decompression blocks
Solution Approach 1:
The compression block performs preliminary action by compressing the data before it enters the SerDes transmission path. This advance compression reduces the amount of data that needs to be transmitted, directly improving data transfer efficiency and reducing test runtime, while the complexity is confined to dedicated compression and decompression blocks that can be optimized independently.
Data Source
AI summary
A method of transferring data from a first circuit block to a second circuit block, includes, in part, sampling the data using a first clock signal during a first cycle, compressing the sampled data at the first circuit block and using a compression ratio. In response to a determination that the compression ratio is equal to or less than a threshold value, selecting the compressed data for transmission to the second circuit block, and selecting a second clock signal for sampling the data during a second cycle. The phase of the second clock signal relative to a phase of the first clock signal is determined in accordance with the compression ratio.