SerDes Receiver Clock Skew Calibration for Multi-Phase Data Recovery
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Solution Overview
Problem
High-speed Serializer-Deserializer (SerDes) receivers face performance degradation due to clock skew, which affects jitter tolerance and noise tolerance, especially as data rates increase and the number of clock phases used by the receiver grows, leading to reduced eye margin and increased vulnerability to errors.
Innovation Solution
The method involves detecting clock skews in SerDes receivers by comparing sampled values with a reference clock signal, generating skew calibration codes to determine whether skews are positive or negative, and adjusting the phase of clock signals using these codes to align them with the reference clock, thereby calibrating and correcting skew.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple clock sequences are used to recover high-speed data, then the receiver can handle higher data rates, but clock skew occurs among the clocks which degrades performance
Solution Approach 1:
The patent applies preliminary action by performing skew calibration before actual data reception. The system pre-adjusts the phase of each clock signal using calibration codes determined from test patterns, so that when real data arrives, the clocks are already optimized for minimal skew, enabling high-speed operation without performance degradation
Solution Approach 2:
The system uses feedback by sampling data with each clock phase and determining skew calibration codes based on the quality of recovered data. The eye diagram parameters and bit error rate measurements provide feedback about clock alignment, which is then used to adjust clock phases iteratively until optimal performance is achieved
2Productivity
If the number of clock phases is increased to support higher data rates, then data rate capability improves, but the possibility of skew increases thereby degrading receiver performance
Solution Approach 1:
The patent segments the clock management problem by treating each clock phase independently. Each of the N clock phases is calibrated separately using individual skew calibration codes, allowing the system to manage complex multi-phase clocking by breaking it down into N independent single-phase calibration problems that can be solved and stored separately
3Adaptability or versatility
If clock skew is present, then the receiver can operate with multiple clocks, but jitter tolerance and noise tolerance are affected negatively
Solution Approach 1:
The system performs preliminary skew calibration to establish optimal clock phases before processing actual data. By pre-determining calibration codes that minimize skew, the system ensures that jitter and noise tolerance are maximized from the start of data reception, allowing reliable multi-clock operation without the adverse effects of uncorrected skew
Data Source
AI summary
Methods and systems for calibrating clock skew in a SerDes receiver. A method includes detecting a skew in a clock with respect to an edge of a reference clock, based on a value sampled by the clock and a value sampled by the reference clock at an edge of a data pattern, for a first Phase Interpolator (PI) code; determining a count of the skew from a de-serialized data word including outcome values obtained based on values sampled by the clock and values sampled by the reference clock at a predefined number of edges of the data pattern; obtaining a skew calibration code corresponding to the first PI code, from a binary variable obtained by accumulating an encoded variable to a previously generated binary variable; and calibrating the skew by performing a positive phase shift or a negative phase shift to the clock based on the skew calibration code.