SERDES Clock Recovery With Sync-Pulse Phase Adjustment
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Solution Overview
Problem
Conventional clock recovery systems in serial data communication are bulky, power-intensive, and lack fine resolution adjustability, making them unsuitable for high-speed data communication and sensitive components.
Innovation Solution
A method and system using a serializer/deserializer (SERDES) circuit to generate a clock signal that alternates between high and low output values, with phase adjustments based on frequency errors determined by sync pulses, allowing precise control of clock frequency through phase slip rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional Phase Locked Loop (PLL) systems are used for clock recovery, then clock recovery effectiveness is improved, but system size, weight, and power requirements increase
Solution Approach 1:
The patent replaces conventional analog PLL circuits with a digital clock recovery system that uses a Numerically Controlled Oscillator (NCO) implemented in software or digital logic. The NCO generates clock signals by digitally adjusting phase and frequency parameters, eliminating the need for analog components like voltage-controlled oscillators and phase detectors. This substitution of mechanical/analog systems with digital/software-based systems reduces power consumption while maintaining clock recovery effectiveness.
2Use of energy by stationary object
If all-digital clock synthesis with delay elements is used, then power consumption is reduced, but fine resolution adjustability is lost and data rate capability is limited to a few hundred megahertz
Solution Approach 1:
The patent implements an NCO that allows dynamic digital adjustment of clock frequency and phase parameters. The NCO uses a phase accumulator and frequency tuning word to precisely control the output clock signal characteristics. This digital parameter control provides fine resolution adjustability comparable to analog PLLs while maintaining the low power consumption of digital systems. The system can achieve frequency resolution down to fractional parts of a clock cycle through digital arithmetic operations.
3Reliability
If conventional clock recovery systems are used, then clock recovery function is achieved, but device complexity and size increase
Solution Approach 1:
The patent implements a multi-functional NCO-based clock recovery system that can perform multiple functions including frequency synthesis, phase adjustment, and clock generation. The same NCO hardware or software module that recovers the clock signal can also generate test patterns, provide timing references for other system functions, and adapt to different data rates. This consolidation of multiple functions into a single digital platform reduces overall system complexity and component count compared to dedicated analog clock recovery circuits.
Data Source
AI summary
Clock recovery from a serial data signal involves using a serializer/deserializer (SERDES) to produce a clock signal which periodically alternates between high and low output clock values. These high and low clock values are generated by outputting for each clock period a series of N digital bits including a plurality of low-level bits to form each low output clock value and a plurality of high-level bits to form each high output clock value. A sync pulse obtained from a sync word present in each frame of the serial data signal is used to periodically determine a frequency error of the clock signal. The frequency error is used as a basis to change a phase of the adjusted clock signal responsive to the frequency error.