SERDES Architecture Reducing Data Transmission Latency

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current data communications architectures, such as IDE/ATA, SCSI, and PCI, face limitations in handling high clock frequency data transmissions, leading to inefficiencies and increased latency due to overhead processing and lack of reliability in processing voluminous data.

Innovation Solution

A data communications architecture employing serializers and deserializers (SERDES) with a data interface that encodes and decodes data using protocols like 8b10b encoding, along with error detection and management features, to reduce latency and enhance reliability by using multiple parallel channels and error detection mechanisms.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If traditional data communication architectures (IDE/ATA, SCSI, PCI) are used, then device compatibility and ease of implementation are maintained, but data transmission speed and bandwidth are limited due to overhead processing

Engineering Contradiction:
Improvedata transmission speedVSAvoidcommunication architecture complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent changes the fundamental parameters of data communication by transitioning from parallel communication architectures to serial communication architectures. This involves changing the data transmission mode from simultaneous multi-bit transmission to sequential bit-by-bit transmission, which eliminates overhead processing and enables higher transmission speeds while maintaining manageable complexity through standardized protocols

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent replaces the mechanical/physical parallel communication system with an electronic serial communication system. By substituting the physical parallel bus structure with electronic serial transmission and encoding schemes, the system achieves higher speeds without proportionally increasing complexity

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Reliability

If overhead processing is included in data communication protocols, then error detection and data integrity are improved, but overall data communication efficiency decreases

Engineering Contradiction:
Improvedata communication reliabilityVSAvoiddata processing throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies preliminary action by pre-calculating and embedding error detection codes (such as 8b10b encoding with disparity control) directly into the data transmission stream before transmission begins. This allows error detection to occur automatically during reception without requiring separate overhead processing steps, thus maintaining both reliability and productivity

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent merges the data transmission function with error detection function into a unified serial communication protocol. The error detection capabilities are integrated directly into the encoding scheme itself, eliminating the need for separate overhead processing and achieving both reliability and high throughput simultaneously

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If high clock frequencies are used for data transmission, then data bandwidth is increased, but latency and signal integrity issues worsen

Engineering Contradiction:
Improvedata bandwidthVSAvoidcommunication latency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent ensures continuous useful action by implementing a continuous serial data stream with embedded clocking and encoding schemes that maintain signal integrity at high frequencies. The uninterrupted bit-by-bit transmission eliminates idle cycles and re-synchronization delays, achieving high bandwidth with minimal latency

Inventive Principle:
Principle #20Continuity of useful action

Solution Approach 2:

The patent employs periodic action through regular clock cycles and structured encoding patterns (such as 8b10b encoding with periodic disparity reversal) that maintain signal integrity at high frequencies. This periodic structure enables reliable high-speed transmission by preventing signal degradation while maintaining continuous data flow

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS7721159B2Passing debug information
Publication Date: 2010.05.18 HEWLETT PACKARD ENTERPRISE DEV LP
  • US7721159B2 patent drawing
  • US7721159B2 patent drawing
  • US7721159B2 patent drawing

AI summary

A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but not limited to generating processing debug information, processing link identification information, injecting errors across communications links and performing error detection.