SERDES Path Delay Balancing via Body Bias Adjustment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for matching parallel data paths between analog and digital domains in SERDES receivers are inadequate, leading to performance limitations and reduced tolerance due to process variations and temperature changes, which are not fully addressed by FET sizing and physical placement techniques.
Innovation Solution
The method involves applying a test signal to selected communication paths to equalize rising and falling edge delays by adjusting body bias voltages, and then adjusting the body bias voltages of other paths to match these delays, using tunable delay elements and a system with multiplexers and latches for calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If FET sizing and physical placement techniques are used to match parallel data paths, then device matching is improved, but device size increases and location restrictions are imposed
Solution Approach 1:
The patent changes the electrical parameter (body bias voltage) of existing delay elements to adjust their delay characteristics. By varying the body bias voltage, the delay of each parallel path can be tuned without changing the physical size or location of the devices, thereby achieving path matching while avoiding the drawbacks of FET sizing and placement techniques.
2Manufacturing precision
If FET sizing and physical placement techniques are used to match parallel data paths, then path delay matching is improved, but process variance compensation is insufficient
Solution Approach 1:
The patent introduces dynamic adjustability to the delay elements by enabling real-time modification of body bias voltages. This dynamic control allows the system to compensate for process variations and environmental changes (such as temperature drift) that static FET sizing and placement techniques cannot address, thereby improving reliability and tolerance.
3Productivity
If delay matching is not properly achieved between analog and digital domains, then system performance is improved, but synchronous tracking is lost
Solution Approach 1:
The patent implements a feedback mechanism where the delay matching status between parallel paths is monitored and used to adjust the body bias voltages of delay elements. This closed-loop control ensures that synchronous tracking is maintained between analog and digital domains, preventing performance degradation that would result from timing mismatches.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for real-time adjustment and synchronization of signal interconnect path delays, enhancing the performance and reliability of SERDES receivers by maintaining synchronous tracking between analog and digital domains, even under varying conditions.
Implementation Method 1
A rising edge delay and a falling edge delay of the test signal is equalized by adjusting a body bias voltage of a delay element configured within the selected communication path
Implementation Method 2
a body bias voltage for one or more of a plurality of delay elements configured within each of the remaining communication paths is adjusted until corresponding rising and falling edge delays thereof match the equalized rising edge delay and falling edge delay
Data Source
AI summary
A method of balancing signal interconnect path delays between an analog domain and a digital domain of an integrated circuit includes applying a test signal to a selected one of a plurality of communication paths between the analog domain and the digital domain. A rising edge delay and a falling edge delay of the test signal is equalized by adjusting a body bias voltage of a delay element configured within the selected communication path. A rising edge delay and a falling edge delay for each of the remaining communication paths is compared with the equalized rising edge delay and falling edge delay of the selected communication path, and a body bias voltage for one or more of a plurality of delay elements configured within each of the remaining communication paths is adjusted until corresponding rising and falling edge delays thereof match the equalized rising edge delay and falling edge delay of the selected communication path.