Serializer-Deserializer Delay Trimming for Skew Tolerance
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Solution Overview
Problem
Integrated circuits (ICs) face performance variations due to temperature, power supply, and fabrication process differences, leading to a significant fallout during testing, as existing trimming methods do not effectively compensate for process-related timing variations in both serializer and deserializer circuits.
Innovation Solution
A method to trim the VCO clock frequency in serializers and apply the same trim value to deserializer clock delays, using binary bits to adjust control voltage and activate fuses or switches, ensuring both circuits operate within specified frequency ranges, thereby addressing process variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If trimming is applied to VCO clock frequency in serializer only, then serializer timing specification is met, but deserializer timing specification is not met due to process variations
Solution Approach 1:
The trim value determined for the serializer VCO clock frequency is universally applied to both the serializer and deserializer timing circuits. This single trim value simultaneously compensates for process variations in both circuits, making the trimming mechanism serve multiple functions and ensuring both serializer and deserializer meet their timing specifications.
Solution Approach 2:
The patent merges the trimming operations of the serializer and deserializer into a single unified process. Instead of separately trimming each circuit, the same trim value is used for both, combining the compensation function and ensuring consistent performance across both timing circuits despite process variations.
2Reliability
If separate trimming is performed for serializer and deserializer, then both timing specifications may be met, but test complexity and time increase
Solution Approach 1:
A single trim value performs the dual function of compensating for process variations in both the serializer VCO clock frequency and the deserializer clock delay. This eliminates the need for separate trimming operations, reducing test time while ensuring both timing specifications are met.
Solution Approach 2:
The trim value is determined in advance during manufacturing testing by measuring only the serializer VCO clock frequency. This preliminary determination of the trim value automatically compensates for both circuits' process variations, eliminating the need for subsequent separate deserializer trimming operations and reducing overall test time.
3Device complexity
If no trim value is applied, then device complexity is low, but process variations cause significant test fallout
Solution Approach 1:
The patent changes the control voltage parameter of the VCO by applying a trim value that adjusts the VCO clock frequency. This parameter change compensates for process variations in both the serializer and deserializer, significantly improving test yield while adding minimal complexity through the use of existing trim mechanisms.
Data Source
AI summary
In an integrated circuit with at least two separate timing circuits, for example both a serializer and a deserializer, a trim value correction factor is developed and applied at the testing of the chip. The correction trim value brings the VCO frequency of the serializer into specifications, but the trim value may also be used to alter the delay between a received clock and data in the deserializer. Since both the serializer and the deserializer were made with the same process, the received clock delay may be corrected by substantially the same correction factor as that applied to the VCO. Illustratively the trim values may be stored on the IC.