SerDes Test Mode for Deterministic Lane Mapping
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Solution Overview
Problem
The non-deterministic nature of mapping between 10 G electrical lanes and 25 G optical lanes in communications networks complicates end-to-end testing, as it is impossible to determine which input lane corresponds to which output lane, and requires expensive 25 G test equipment for serial lane testing.
Innovation Solution
Implementing a multiplexing stage in serializer ICs and a demultiplexing stage in deserializer ICs with synchronizing flip flops and multiplexers to deterministically map parallel data signals to serial data signals and vice versa, using a test signal to enable correlation and locking, allowing for end-to-end testing with lower-speed test equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If non-deterministic mapping between 10 G electrical lanes and 25 G optical lanes is used, then device complexity is reduced, but testing difficulty increases and measurement precision is lost
Solution Approach 1:
The patent applies preliminary action by inserting a known test signal pattern into specific parallel lanes before serialization. This test signal is processed through the serializer and deserializer in advance, allowing the receiving end to correlate the test signal with specific output lanes, thereby establishing deterministic mapping relationships before actual data transmission begins
Solution Approach 2:
The patent uses a test signal as an intermediary element between the parallel input lanes and serial output lanes. This test signal acts as a marker or identifier that traverses through the serialization and deserialization process, enabling the establishment of correspondence relationships between input and output lanes without requiring complex deterministic mapping logic in the normal data path
2Measurement precision
If 25 G test equipment is used for serial lane testing, then measurement precision is improved, but cost increases
Solution Approach 1:
The patent creates a copy of the test signal at the receiving end by correlating the received test signal with the known transmitted pattern. This allows the test equipment to work at lower speeds (10 G) while still accurately measuring the high-speed (25 G) serial lane performance, as the test signal copying and correlation process enables precise measurement without requiring expensive 25 G test equipment
Solution Approach 2:
The patent changes the testing parameter from direct high-speed serial signal analysis to low-speed test signal correlation and comparison. By transforming the measurement approach from operating at 25 G to operating at 10 G with signal processing, the system achieves the same measurement precision using lower-cost, lower-speed test equipment
Data Source
AI summary
Serializer, deserializer, and/or serdes ICs are configured to support one or more test modes to enable end-to-end testing in communication links in which the ICs are implemented. To support the end-to-end testing, the ICs can include a multiplexing stage with means for deterministically mapping a plurality of input parallel data signals to at least one output serial data signal and/or a demultiplexing stage with means for deterministically mapping at least one input serial data signal to a plurality of output parallel data signals. When used in combination in a communication link, the means included in the multiplexing stage and demultiplexing stage deterministically map specific input parallel data signals to specific output parallel data signals.