SERDES DFT Encoding for Deterministic Latency
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Solution Overview
Problem
Current SERDES-based DFT systems face challenges in deterministic data latency, leading to non-deterministic packet flow and increased complexity and cost due to the need for packet processing circuitry and decoding, which limits the ability to test large and complex integrated circuits efficiently.
Innovation Solution
The implementation of an encoding technique that eliminates the need for decoding circuitry and a packet processing technique to achieve deterministic timing of response packets, allowing for high-speed testing with fewer pins on the DUT and enabling existing ATEs without packet processing circuitry to be used.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If packet processing circuitry and decoding circuitry are used in SERDES-based DFT systems, then data can be transmitted over high-speed I/O lanes, but device complexity and cost increase
Solution Approach 1:
The patent extracts and eliminates the decoding circuitry from the DUT by using an encoding technique that maps test response data directly into the SERDES protocol format. This allows high-speed data transmission over I/O lanes without requiring complex packet processing or decoding circuitry in the device under test, thereby reducing device complexity while maintaining high transmission speed capability
Solution Approach 2:
The patent introduces an intermediary encoding technique as a mediator between the test response data and the SERDES transmission protocol. This encoding layer translates the test response data into a format compatible with high-speed I/O lanes, enabling direct transmission without requiring complex packet processing circuitry in the DUT
2Productivity
If packet processing circuitry is implemented, then high-speed testing is enabled, but ATE cost and complexity increase
Solution Approach 1:
The patent enables the DUT to perform self-service by incorporating the encoding functionality directly into the device under test. This allows the DUT to prepare and transmit test response data in the correct format for high-speed I/O lanes without requiring complex packet processing capabilities in the ATE, thereby maintaining high testing productivity while reducing ATE complexity
Solution Approach 2:
Instead of having the ATE perform complex packet processing and decoding operations to handle high-speed data, the patent inverts the approach by having the DUT perform the encoding operation. This inversion transfers the complexity from the ATE to the DUT, allowing existing ATEs without packet processing circuitry to be used for high-speed testing
3Productivity
If more pins are used on the DUT for high-speed I/O interfaces, then testing capability is improved, but device resource consumption increases
Solution Approach 1:
The patent changes the data representation parameter by encoding test response data directly into the SERDES protocol format. This parameter change allows the use of existing high-speed I/O lanes with minimal pins on the DUT, as the encoding handles the data formatting rather than requiring additional dedicated test pins, thereby improving testing capability without proportionally increasing the number of pins required
Data Source
AI summary
Test packets may be received at a design under test (DUT) from an automated test equipment (ATE) over a serializer/deserializer (SERDES) connection between the ATE and the DUT. The test packets may include test pattern data to test the DUT. The test pattern data may be applied to the DUT using a set of scan chains and test response data corresponding to the test pattern data may be obtained. The test response data may be received by a circuit in the DUT at irregular time intervals. Response packets may be sent to the ATE by the circuit in the DUT at regular time intervals, where the response packets may include a portion of the test response data (which may be encoded using an encoding technique), and where the response packets may be sent to ATE over the SERDES connection.