SerDes Die Stacking for High-Speed Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Legacy die-to-die interconnects with large bus sizes face issues of increased die size, latency, and power requirements due to the need for wider signal transmission, which is constrained by bump pitch limitations.
Innovation Solution
Implementing ultra-thin SerDes chiplets at fine pitch for high-speed signal transmission, decoupling SerDes blocks from the main die using through-silicon vias and double-sided interconnects, allowing optimized process technologies for logic/memory and RF applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If legacy die-to-die interconnects are used with large bus sizes, then signal transmission capability is improved, but die size increases
Solution Approach 1:
The patent segments the SerDes functionality into a separate ultra-thin die that can be stacked on top of the main logic die. This segmentation allows the logic die to maintain a small area while the SerDes die provides high-capacity signal transmission through vertical interconnects, resolving the contradiction between transmission capability and die size.
Solution Approach 2:
The patent transitions from planar signal transmission to three-dimensional vertical transmission by stacking the SerDes die on top of the logic die. This dimensional change enables high-bandwidth communication through the vertical axis (using through-silicon vias and microbumps) rather than requiring large lateral area on the same die plane.
2Quantity of substance
If legacy die-to-die interconnects are used with large bus sizes, then signal transmission capability is improved, but latency increases
Solution Approach 1:
By moving signal transmission to the vertical dimension through die stacking, the patent achieves shorter transmission paths compared to lateral routing on large dies. The ultra-thin SerDes die minimizes the vertical distance for signal traversal, reducing propagation delay and latency while maintaining high transmission capability.
3Quantity of substance
If legacy die-to-die interconnects are used with large bus sizes, then signal transmission capability is improved, but power requirements increase
Solution Approach 1:
The patent segments power management responsibilities between the logic die and SerDes die. The ultra-thin SerDes die can be optimized with dedicated power-efficient high-speed transceiver circuits, while the logic die focuses on computation. This segmentation allows each die to be optimized for its specific function, reducing overall power requirements for high-capacity transmission.
4Quantity of substance
If bump pitch is reduced to accommodate more signals, then signal transmission capability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent uses moderate-pitch microbumps for vertical die-to-die interconnects, avoiding the need for extremely fine-pitch lateral bumping. The ultra-thin SerDes die design allows for larger, more manufacturable bump pitches while still achieving high signal capacity through the vertical stacking architecture and efficient use of through-silicon via interconnects.
Data Source
AI summary
In embodiments, a semiconductor package may include a first die and a second die. The package may additionally include a serializer/deserializer (SerDes) die coupled with the first and the second dies. The SerDes die may be configured to serialize signals transmitted from the first die to the second die, and deserialize signals received from the second die. Other embodiments may be described and/or claimed.