SERDES Receiver DSP Filter Architecture for Reflection Cancellation

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Conventional DSP-based serializer deserializers face challenges in maintaining high efficiency and reducing power and chip area while handling densely-populated channels with reflections, leading to increased latency and complexity, which affects jitter tolerance and bit-error-rate performance.

Innovation Solution

Implementing a low-power, low-area architecture with a cascaded combination of three filters and an optional interpolator, including a short RX-FFE, reflection canceller FIR filter, and noise-shaping PR FIR filter, to achieve fast-timing recovery and reflection-cancellation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a long feed-forward equalizer (FFE) is used to equalize reflections at long delays, then equalization performance is improved, but power consumption and chip area increase

Engineering Contradiction:

Improveequalization performanceVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent divides the equalization function into two separate modules: a feed-forward equalizer (FFE) for equalizing current and past symbols, and a decision-feedback equalizer (DFE) for canceling reflections from past decisions. This segmentation allows each module to be optimized independently, reducing the total number of taps required compared to a single long FFE, thereby lowering power consumption and chip area while maintaining equalization performance.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements a decision-feedback equalizer (DFE) that uses feedback from previously decided symbols to cancel reflections. The DFE taps are activated based on detected reflections, allowing the system to target and cancel specific reflection paths without requiring a uniformly long FFE. This feedback mechanism improves equalization efficiency by focusing computational resources only where needed, reducing overall power consumption.

Inventive Principle:

Principle #23Feedback

2Reliability

If a long feed-forward equalizer (FFE) is used to equalize reflections at long delays, then equalization performance is improved, but chip area increases

Engineering Contradiction:

Improveequalization performanceVSAvoidchip area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Inventive Principle:

Principle #23Feedback

3Reliability

If more active taps are used to equalize attenuated high-frequency content, then signal quality is improved, but power consumption and chip area increase

Engineering Contradiction:

Improvesignal qualityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The patent employs adaptive tap activation where the number and position of active taps in both FFE and DFE are dynamically adjusted based on channel conditions and detected reflection characteristics. This parameter adaptation allows the system to use more taps only when and where needed to equalize attenuated high-frequency content, rather than maintaining a uniformly high tap count across all positions, thereby optimizing the balance between signal quality and power consumption.

Inventive Principle:

Principle #35Parameter changes

4Reliability

If a long feed-forward equalizer (FFE) is used, then equalization performance is improved, but latency increases causing loss of margin in jitter-tolerant environments

Engineering Contradiction:

Improveequalization performanceVSAvoidlatency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent divides the equalization function into two separate modules: a feed-forward equalizer (FFE) for equalizing current and past symbols, and a decision-feedback equalizer (DFE) for canceling reflections from past decisions. This segmentation allows the FFE to operate with fewer taps for immediate equalization, reducing latency, while the DFE handles long-delay reflections asynchronously, maintaining equalization performance without adding to the critical timing path.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Inventive Principle:

Principle #23Feedback

5Loss of time

If a separate shorter FFE is dedicated to the timing recovery path, then timing recovery latency is reduced, but redundancy and complexity are added

Engineering Contradiction:

Improvetiming recovery latencyVSAvoidcircuit complexity

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The patent makes the feed-forward equalizer (FFE) multi-functional by using its output for both data equalization and timing recovery. The FFE is positioned in the signal path such that its equalized output can be simultaneously fed to the DFE for data recovery and to the timing recovery circuit. This eliminates the need for a separate dedicated FFE for timing recovery, reducing redundancy and circuit complexity while maintaining low latency for timing recovery.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentEP4167535B1Efficient architecture for high-performance DSP-based serdes

Publication Date: 2025.11.26 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD

Figure 1
Figure 2
Figure 3

AI summary

It is described a digital signal processing (DSP) device comprising (a) a first filter configured to equalize channel dispersion associated with signal transmission; (b) a second filter configured to cancel channel reflections; and (c) a third filter configured to at least filter noise. The DSP device comprises a receiver DSP of a serializer deserializer (SERDES). Further, described is a system comprising (a) an analog-to-digital converter (ADC) configured to convert an analog signal from an analog front-end (AFE) circuit; (b) a first equalizer configured to equalize channel dispersion of a transmission medium coupled to the AFE circuit; (c) a reflection canceller configured to cancel channel reflections associated with the transmission medium; and (d) a second equalizer configured to remove an inter-symbol interference (ISI). The AFE circuit is configured to receive analog signals transmitted by a serializer-deserializer (SERDES) transmitter through the transmission medium. Furthermore, it is described a serializer deserializer (SERDES) receiver.