SERDES Receiver DSP Filter Architecture for Reflection and Noise Control
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Solution Overview
Problem
Conventional high-speed digital signal processing (DSP)-based serializer deserializers (SERDES) face challenges in reducing power usage and chip area while maintaining high efficiency, particularly in densely populated and low-cost channels, due to long feed-forward equalizers and decision-feedback equalizers that increase latency and complexity, leading to sub-optimal signal quality and increased bit-error-rate.
Innovation Solution
A low-power, low-area architecture is implemented with a cascaded combination of three filters and an optional interpolator, including a short receive FFE filter for low-latency timing recovery, a reflection canceller FIR filter, and a noise-shaping programmable-response FIR filter, which reduces dynamic range and active taps, enabling efficient noise shaping and reflection cancellation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a long feed-forward equalizer (FFE) and short decision-feedback equalizer (DFE) are used to equalize reflections in practical channels, then the equalization performance is improved, but the power consumption and chip area of the DSP increase
Solution Approach 1:
The patent divides the equalization function into two independent modules: a long FFE for reflection cancellation and a short DFE for ISI mitigation. This segmentation allows each module to be optimized separately, reducing the total number of taps needed compared to a single long equalizer, thereby lowering power consumption and chip area while maintaining equalization performance.
Solution Approach 2:
The patent extracts the reflection cancellation function from the traditional single equalizer structure and implements it as a separate long FFE module. This extraction allows the DFE to be kept short by removing the burden of reflecting equalization, reducing overall complexity and power usage while maintaining the ability to handle both reflections and ISI.
2Reliability
If a long feed-forward equalizer (FFE) is used to equalize reflections at long delays, then the equalization capability is improved, but the latency increases causing loss of margin in highly integrated environments
Solution Approach 1:
The patent segments the equalization tasks by time and function: the long FFE handles historical reflections with large delays, while the short DFE handles recent ISI with minimal delay. This segmentation allows the system to achieve comprehensive equalization capability without requiring the entire signal path to wait for the longest FFE processing, thus reducing effective latency for timing-critical operations.
3Speed
If a separate shorter FFE is dedicated to the timing recovery path to reduce latency, then the timing recovery speed is improved, but redundancy and complexity are added to the system
Solution Approach 1:
The patent makes the long FFE serve multiple functions: it performs both reflection cancellation for data equalization and provides equalized samples for timing recovery. This multi-functionality eliminates the need for a separate shorter FFE in the timing path, reducing system complexity and redundancy while maintaining fast timing recovery capability through the short DFE module.
Data Source
AI summary
A digital signal processing (DSP) device includes a first fitter to equalize channel dispersion associated with signal transmission through a medium, a second filter to cancel channel reflections, and a third filter to at least reduce noise. The DSP device is a receiver DSP of the SERDES.