Fibre Channel SERDES Elastic FIFO Buffer Jitter Control
Solution Overview
Problem
Conventional SERDES devices in Fibre Channel storage area networks face challenges with clock jitter accuracy, which is insufficient to support data rates higher than 2 Gbps, as the clock signal driving the transmitter has significant jitter, failing to meet the required clock jitter standards for higher data transmission rates.
Innovation Solution
An elastic first-in first-out (FIFO) buffer system that receives parallel data according to a first clock signal and transmits it according to a second independent clock signal, with a buffer controller managing data storage cells to prevent overruns and underruns by inserting or deleting fill words based on threshold levels, ensuring accurate data transmission at rates greater than or equal to 4 Gbps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional FIFO buffer is used to transmit data at higher rates, then data transmission speed can be increased, but clock jitter exceeds the acceptable threshold (greater than 100 ppm)
Solution Approach 1:
The patent applies dynamics by making the buffer occupancy adjustable rather than fixed. The buffer controller dynamically modifies the number of buffer occupancy bits based on the relationship between transmitter and receiver clock rates, allowing the system to adapt to varying clock jitter conditions while maintaining high data transmission rates
Solution Approach 2:
The patent changes the parameter of buffer occupancy from a fixed value to a variable value that depends on clock rate relationships. By adjusting the buffer occupancy bits according to the ratio of transmitter clock rate to receiver clock rate, the system optimizes both transmission speed and clock jitter performance
2Reliability
If buffer occupancy is increased to prevent data loss, then data transmission reliability improves, but buffer overflow and underflow errors increase
Solution Approach 1:
The patent implements feedback by continuously monitoring the relationship between transmitter and receiver clock rates and adjusting buffer occupancy accordingly. The buffer controller uses feedback about clock rate relationships to dynamically set the number of buffer occupancy bits, preventing both overflow and underflow conditions
Solution Approach 2:
The buffer occupancy is made dynamic rather than static, allowing the system to adjust the buffer depth in real-time based on actual operating conditions. This dynamic adjustment prevents the system from operating in states that would cause overflow or underflow errors
Data Source
AI summary
A data transfer system having a method and computer program therefor comprises a buffer adapted to receive parallel data according to a first clock signal, and to transmit the parallel data according to a second clock signal, wherein the buffer comprises a plurality of storage cells adapted to store the parallel data received by the buffer; a buffer controller adapted to cause the buffer to transmit an additional predetermined amount of the parallel data when a number of the storage cells storing the parallel data received by the buffer but not yet transmitted by the buffer is less than or equal to a first threshold; wherein the buffer controller is further adapted to cause the buffer to delete a predetermined amount of the parallel data when a number of the storage cells storing the parallel data received by the buffer but not yet transmitted by the buffer is greater than or equal to a second threshold; and a serializer adapted to convert the parallel data transmitted by the buffer to serial data, and to transmit the serial data according to the second clock signal; wherein the first and second clock signals are independent.