SerDes Equalization for Reflective Short PCB Channels
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-rate SerDes blocks designed with standard channel assumptions and parameter limits exhibit inadequate performance on low-loss channels due to significant impedance mismatches and reflection-induced inter-symbol interference (ISI), leading to poor equalization and increased bit error ratios.
Innovation Solution
Implementing a serializer and deserializer with a pre-equalizer that attenuates frequency components at half the symbol rate relative to one third, and a controller that adjusts equalizer coefficients or bandwidth to artificially suppress high-frequency components based on channel reflection strength, thereby mitigating ISI and improving signal quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard equalization techniques are used for high-rate SerDes blocks, then equalization performance is improved for typical channels, but performance deteriorates on low-loss channels with impedance mismatches due to reflection-induced ISI
Solution Approach 1:
The patent inverts the conventional equalization approach by applying pre-emphasis that attenuates high-frequency components rather than boosting them. The pre-equalizer uses inverted coefficient signs (negative pre-cursor and post-cursor coefficients) to create artificial attenuation of frequency components at half the symbol rate, which counteracts the reflection-induced ISI caused by impedance mismatches on low-loss channels.
Solution Approach 2:
The patent changes the equalization parameters by introducing adjustable pre-cursor and post-cursor coefficients that can be optimized for low-loss channels. The system modifies the frequency response characteristics by attenuating specific frequency components (particularly at half the symbol rate) rather than following standard equalization curves, allowing adaptation to channels with significant reflections.
2Strength
If high-frequency components are boosted to combat channel loss, then signal strength is improved, but reflection-induced ISI increases on low-loss channels with impedance mismatches
Solution Approach 1:
Instead of boosting high-frequency components as in conventional equalization, the patent applies pre-emphasis with inverted characteristics that attenuate high-frequency components. The pre-equalizer uses negative coefficients to reduce the amplitude of frequency components at half the symbol rate, preventing these components from causing excessive ISI through reflections while maintaining adequate signal strength.
Solution Approach 2:
The patent converts the harmful effect of high-frequency components causing ISI into a benefit by deliberately attenuating them through the pre-equalizer. The artificial attenuation of high-frequency components prevents reflection-induced ISI, and the system benefits from reduced interference while maintaining signal integrity through the inverted equalization approach.
Data Source
AI summary
An illustrative short, high-rate communications link includes a serializer that provides a signal having a symbol rate of at least 10 GHz; and a deserializer that receives the signal via a printed circuit board (“PCB”) trace coupled to the serializer with a first impedance mismatch and coupled to the deserializer with a second impedance mismatch. At least one of the serializer and deserializer includes an equalizer that attenuates a frequency component of the signal at half of the symbol rate relative to a frequency component of the signal at one third of the symbol rate. Though such attenuation may reduce signal-to-noise ratio, an improved communications performance may nevertheless be achieved by suppression of signal reflections.