Communications Link Performance Analyzer for SerDes FEC Evaluation

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Solution Overview

Problem

High-speed serializer and de-serializer modules face challenges in specifying coding requirements and minimum performance characteristics for forward error correction, making it difficult for users to assess the suitability of communications links for high-data-rate applications.

Innovation Solution

A communications link performance analyzer that transmits a predetermined bit stream across a physical link, derives a received bit stream, and generates performance measures based on symbol error counts using a debug module with a bit counter, error counter, and aggregator, enabling evaluation of link performance with and without forward error correction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If SerDes modules operate at high data rates (e.g., 25 Gbit/s), then data transmission speed is improved, but bit error rate increases due to physical media interference and circuit limitations

Engineering Contradiction:
Improvedata transmission rateVSAvoidbit error rate
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent introduces an intermediary performance analyzer system that sits between the SerDes module and the physical media. This analyzer includes a transmitter that sends test signals through the physical link, a receiver that captures and analyzes the signals, and generates performance metrics. This intermediary system enables precise measurement and characterization of link performance without directly transmitting actual data, thereby resolving the contradiction by providing a dedicated testing pathway that doesn't interfere with normal high-speed data transmission while accurately measuring error rates.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If Forward Error Correction (FEC) is implemented to reduce bit error rates, then reliability is improved, but the complexity of specifying coding requirements and evaluating performance increases

Engineering Contradiction:
Improvebit error rateVSAvoidcoding requirement specification complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The performance analyzer is designed to automatically characterize link performance and generate comprehensive reports without requiring manual configuration of FEC coding parameters or manual analysis of error rates. The system self-configures test parameters, automatically transmits test signals, measures performance metrics including error rates with and without FEC, and generates detailed performance characterization reports. This self-service capability eliminates the need for users to manually specify complex coding requirements, thereby resolving the contradiction by making the system intelligent and automated rather than requiring manual expertise in FEC configurations.

Inventive Principle:
Principle #25Self-service

3Adaptability or versatility

If multiple configuration parameters for link and FEC code are available, then adaptability is improved, but ease of operation deteriorates due to difficulty in judging suitability

Engineering Contradiction:
Improvelink configuration flexibilityVSAvoiduser ability to assess link suitability
Core Design Contradiction:
Adaptability or versatilityVSEase of operation

Solution Approach 1:

The performance analyzer implements comprehensive feedback mechanisms that automatically measure and report link performance across multiple configuration parameters. The system tests various link settings and FEC configurations, then provides detailed feedback reports including performance metrics, error rate analysis, and suitability assessments. This feedback loop enables users to objectively evaluate different configurations without needing to manually calculate or interpret complex parameters, resolving the contradiction by transforming the complexity of multiple configuration options into actionable, easy-to-interpret performance data that guides optimal configuration selection.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS10063305B2Communications link performance analyzer that accommodates forward error correction
Publication Date: 2018.08.28 CREDO TECHNOLOGY GROUP LTD
  • US10063305B2 patent drawing
  • US10063305B2 patent drawing
  • US10063305B2 patent drawing

AI summary

Illustrative communications link performance analyzer methods and modules that accommodate FEC. In at least some embodiments, a method for characterizing communications link performance includes: (A) transmitting a predetermined bit stream across a physical communications link to produce a receive signal; (B) deriving a received bit stream from the receive signal with a receiver, the receiver including an embedded debug module having: (1) a bit counter dividing the received bit stream into symbols and frames; (2) an error counter determining a symbol error count for each frame; and (3) an aggregator obtaining at least one performance-related statistic from the symbol error counts; (C) generating a performance measure based on the at least one performance-related statistic; and (D) displaying a visual representation of the performance measure.