SerDes FFE Synchronization for Glitch-Free 2-to-1 Serialization
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Solution Overview
Problem
In serializer/deserializer (SerDes) systems, the feed forward equalization (FFE) enable signal is asynchronous with the data domain, leading to glitches at the FFE selection multiplexer, which cannot be filtered due to the absence of full rate clocks, resulting in false detection in receiver squelch circuits.
Innovation Solution
The FFE enable signal is synchronized to the half rate data domain by introducing a latency generation circuit that creates a latency equal to the serializer's latency, allowing the FFE transition glitch to be filtered at a final 2-to-1 serializer, ensuring FFE is turned ON/OFF exactly at high speed data boundaries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the FFE enable signal is used asynchronously with the data domain, then the FFE can be turned on/off during high speed bursts, but glitches occur at the FFE selection multiplexer that cannot be filtered
Solution Approach 1:
A latency generation circuit is introduced as an intermediary component between the asynchronous FFE enable signal and the FFE selection multiplexer. This circuit synchronizes the enable signal to the half rate data domain by adding controlled latency, thereby eliminating glitches while preserving the ability to turn FFE on/off during high speed bursts.
Solution Approach 2:
The enable signal is transformed from the full rate data domain to the half rate data domain by introducing controlled latency. This parameter change in the signal's temporal characteristics allows synchronization with the multiplexer clock domain, eliminating glitches while maintaining functional flexibility.
2Object-generated harmful factors
If full rate clocks are used for filtering glitches, then glitches can be filtered, but clock loading increases and high speed path layout is impacted
Solution Approach 1:
Instead of using full rate clocks for filtering, the solution changes the operational parameter to half rate clocks. The latency generation circuit synchronizes the enable signal to the half rate domain, allowing glitch filtering to occur at the final 2-to-1 serializer using lower frequency clocks, thereby reducing clock loading and simplifying high speed path layout.
3Object-generated harmful factors
If the FFE enable signal is synchronized to half rate domain with latency, then glitches are filtered and false detections are reduced, but latency is introduced in the enable signal path
Solution Approach 1:
The latency generation circuit performs preliminary synchronization of the FFE enable signal to the half rate domain before the signal reaches the FFE selection multiplexer. This advance timing adjustment ensures that the enable signal transitions are properly aligned with the data domain, preventing false detections in receiver squelch circuits while the latency is absorbed in the enable path.
Data Source
AI summary
There is provided a system and a method for filtering out glitches in a SerDes transmitter. The SerDes transmitter includes a latency generation block, and a 2-to-1 serializer. The latency generation block is configured to synchronize a feed forward equalization (FFE) signal to a half rate domain by creating a latency in a FFE enable signal, and provide the synchronized FFE enable signal to a plurality of synchronized FFE selection multiplexers. The SerDes transmitter further includes a 2-to-1 serializer that is configured to filter out a glitch using the synchronized FFE enable signal in the half rate domain.