DSP SerDes Filter Architecture for Long-Reach ISI and Reflection Cancellation

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Solution Overview

Problem

Conventional DSP-based serializer-deserializers (SERDES) face challenges in maintaining high efficiency and reducing power and area consumption while effectively handling long-reach transmission channels with significant inter-symbol interference (ISI) and reflection, leading to increased complexity and latency.

Innovation Solution

Implementing a low-power, low-area architecture with a cascaded combination of three filters: a short RX-FFE, a reflection canceller FIR filter, and a noise-shaping PR FIR filter, along with an optional interpolator, to achieve fast-timing recovery and reflection-cancellation, while retaining FFE and DFE-like noise shaping.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a long feed-forward equalizer (FFE) with many taps is used to equalize reflections at long delays, then the equalization performance is improved, but the power consumption and chip area increase

Engineering Contradiction:

Improveequalization performanceVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The patent divides the equalization function into two separate modules: a feed-forward equalizer (FFE) for pre-cursor ISI and a decision-feedback equalizer (DFE) for post-cursor ISI and reflections. This segmentation allows each module to be optimized independently, with the DFE using past decisions to cancel reflections without requiring an excessively long FFE, thereby reducing overall power consumption while maintaining equalization performance.

Inventive Principle:

Principle #1Segmentation

2Reliability

If a long feed-forward equalizer (FFE) with many taps is used to equalize reflections at long delays, then the equalization performance is improved, but the chip area increases

Engineering Contradiction:

Improveequalization performanceVSAvoidchip area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent divides the equalization function into two separate modules: a feed-forward equalizer (FFE) for pre-cursor ISI and a decision-feedback equalizer (DFE) for post-cursor ISI and reflections. This segmentation allows each module to be optimized independently, with the DFE using past decisions to cancel reflections without requiring an excessively long FFE, thereby reducing overall chip area while maintaining equalization performance.

Inventive Principle:

Principle #1Segmentation

3Reliability

If more FFE taps are added to reduce inter-symbol interference (ISI) in long-reach transmission, then the ISI reduction is improved, but the power consumption and chip area increase

Engineering Contradiction:

ImproveISI reductionVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The patent segments the ISI cancellation function between FFE (handling pre-cursor ISI) and DFE (handling post-cursor ISI). This allows the FFE to remain relatively short while the DFE compensates for the remaining ISI using feedback from previously decided symbols, thereby achieving effective ISI reduction without the power penalty of a long FFE.

Inventive Principle:

Principle #1Segmentation

4Reliability

If a long feed-forward equalizer (FFE) is used to equalize reflections, then the reflection cancellation is improved, but the processing latency increases

Engineering Contradiction:

Improvereflection cancellationVSAvoidprocessing latency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent divides the equalization function into FFE for pre-cursor ISI and DFE for post-cursor ISI and reflections. The DFE structure allows reflection cancellation to be performed using feedback from previously decided symbols, avoiding the need to wait for the entire long FFE processing to complete, thereby reducing processing latency while maintaining reflection cancellation capability.

Inventive Principle:

Principle #1Segmentation

5Speed

If a separate shorter FFE is dedicated to the timing recovery path, then the timing recovery speed is improved, but the device complexity and redundancy increase

Engineering Contradiction:

Improvetiming recovery speedVSAvoiddevice complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent makes the DFE serve multiple functions: it cancels post-cursor ISI, cancels reflections, and provides equalized output for timing recovery. This multi-functionality eliminates the need for a separate FFE in the timing recovery path, reducing device complexity and redundancy while maintaining fast timing recovery capability through the DFE's processed output.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250357917A1Efficient architecture for high-performance DSP-based long-reach serdes

Publication Date: 2025.11.20 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD

AI summary

A digital signal processing (DSP)-based serializer-deserializer (SERDES) includes a first filter configured to mitigate inter-symbol interference (ISI) attributed to dispersion associated with a long-reach transmission medium. The SERDES includes a second filter configured to shape the ISI. The SERDES includes also includes a third filter coupled in parallel with the second filter and configured to reduce ISI attributed to reflections associated to both near-zero delays and long delays.