SERDES Flank Timing Measurement for High-Resolution Signal Detection
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Solution Overview
Problem
Conventional time measurement systems in digital circuits face limitations such as low channel count, high power consumption, and complex maintenance due to their low temporal resolution and resource-intensive implementations, making precise measurement of signal flanks challenging, especially in applications like traffic monitoring.
Innovation Solution
The approach utilizes Serdes cells with a high sampling rate to generate data words from signal flanks, employing multiple Serdes cells with phase-shifted scanning clocks to achieve higher temporal resolution and precision in determining the time of signal flanks, allowing for precise measurement of signal changes and pulse widths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the system clock frequency is increased to improve time resolution, then the temporal resolution of signal flank detection is improved, but the power consumption and Place & Route times significantly increase
Solution Approach 1:
The patent divides the time measurement function into multiple independent Serdes channels, each capable of autonomous time measurement. This segmentation allows parallel processing of multiple signals without requiring a single high-frequency system clock, thereby reducing overall power consumption while maintaining high temporal resolution through the inherent high sampling rate of Serdes cells
2Measurement precision
If the system clock frequency is increased to improve time resolution, then the temporal resolution of signal flank detection is improved, but the Place & Route times significantly increase
Solution Approach 1:
The patent segments the time measurement functionality across multiple Serdes channels, each operating independently with its own deserializer and time measurement circuitry. This modular segmentation simplifies the Place & Route process compared to a monolithic high-frequency design, as each channel can be implemented as a self-contained unit with standardized interfaces
Solution Approach 2:
The patent employs Serdes cells that serve dual purposes: their primary function for high-speed data transmission and their secondary function for precise time measurement. This multi-functionality eliminates the need for separate dedicated time measurement circuits, reducing overall device complexity and simplifying implementation in programmable logic devices
3Measurement precision
If time measurement circuits are added to improve measurement precision, then the temporal resolution is improved, but the channel count is limited and additional costs and power consumption are incurred
Solution Approach 1:
The patent leverages the inherent capabilities of Serdes cells to perform both high-speed data transmission and precise time measurement functions. By utilizing the deserializer's sampling mechanism for time measurement, the system gains multiple measurement channels without adding dedicated time measurement circuits, thereby increasing channel count while avoiding additional power consumption and cost
Solution Approach 2:
The patent enables Serdes channels to self-measure time by utilizing their own internal sampling clock and deserializer logic. Each Serdes channel independently determines the time of signal flanks using its own resources, eliminating the need for external time measurement circuits and expanding the effective channel count for time measurement
4Measurement precision
If internal runtime members are used for time measurement to improve precision, then the measurement capability is integrated, but the resources required for multiple input signals are excessive and implementation results vary significantly
Solution Approach 1:
The patent makes the Serdes cell's deserializer serve a dual function: its primary role in high-speed data reception and its secondary role as a time measurement instrument. This universal usage of existing high-frequency sampling infrastructure provides precise time measurement capability across multiple channels without requiring additional dedicated resources for each measurement point
Solution Approach 2:
The patent changes the operational parameters of the Serdes deserializer to optimize it for time measurement applications. By adjusting the sampling clock frequency and phase relationships, the system achieves high temporal resolution for multiple input signals using the same hardware resources, thereby reducing overall device complexity and resource consumption
Data Source
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AI summary
The invention relates to a method (700) for determining a time of a flank (200) in a signal (132), wherein the method (700) comprises a step of reading (710) the signal (132) and has a master clock (210) for operating a digital evaluation unit (125) for evaluating the time of the flank (200). The method (700) also comprises a step of forming (720) a data word (220) representing the signal (132), using a deserializer (310) of a SERDES cell (300), wherein the data word (220) has a plurality of bits, and wherein a sampling clock (205) is applied to the the SERDES cell (300) for sampling the signal (132), which sampling clock is higher than the master clock (210), wherein one flank or two flanks of the sampling clock (205) are used for sampling the signal (132). Finally, the method (700) comprises a step of determining (730) the time of the flank (200) in the signal (132) using the data word (220) and the master clock (210) in the evaluation unit (125).