SERDES Flank Timing for High-Resolution Signal Measurement
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Solution Overview
Problem
Conventional transit time measurement systems face limitations in time resolution due to low system clock rates, leading to increased power consumption, resource-intensive implementations, and differential non-linearities, making precise flank detection in signals challenging, especially in digital circuits.
Innovation Solution
The method employs SERDES cells with higher sampling clock rates than the master clock rate to form data words, allowing for precise determination of signal flanks by utilizing both flanks of the sampling clock rate and phase-shifted sampling clock rates, combined with synchronization and adjustable delay elements to enhance precision and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the system clock rate is increased to improve time resolution, then measurement precision is improved, but power consumption and current consumption increase significantly
Solution Approach 1:
The patent segments the time measurement function by using multiple independent time measuring circuits, each handling specific signal channels. This allows parallel processing at lower clock rates rather than requiring a single high-speed clock for all channels, thereby reducing overall power consumption while maintaining measurement precision.
Solution Approach 2:
The patent implements dynamic clock gating and selective activation of time measuring circuits based on signal presence and measurement requirements. Clock signals are enabled only when needed for specific channels, reducing unnecessary power consumption while maintaining high time resolution when measurements are actually performed.
2Measurement precision
If the system clock rate is increased to improve time resolution, then measurement precision is improved, but device complexity and implementation difficulty increase
Solution Approach 1:
The patent divides the measurement system into multiple independent time measuring circuits, each operating at lower clock rates. This segmentation simplifies the design and implementation of each individual circuit while achieving high overall resolution through parallel operation and coordinated timing.
Solution Approach 2:
The patent replaces a single high-speed mechanical/clock-based timing system with multiple lower-speed digital timing circuits that use logic-based time stamping and counter mechanisms. This substitution reduces the complexity requirements for high-frequency clock distribution and synchronization.
3Productivity
If additional time measuring circuits are added to evaluate more flanks, then productivity is improved, but device complexity and cost increase
Solution Approach 1:
The patent uses multiple segmented time measuring circuits that can be independently configured for different signal channels and flank types. This modular approach allows the system to evaluate multiple flanks simultaneously across different channels without requiring a single complex circuit, thereby improving productivity while managing complexity through standardization.
Solution Approach 2:
The patent designs time measuring circuits with universal functionality that can detect and measure both rising and falling flanks across multiple signal channels. Each circuit is configured to handle various measurement scenarios, reducing the need for specialized circuits for each flank type and improving overall system productivity without proportional increases in complexity.
4Device complexity
If internal transit time elements are used for time measurement, then device complexity is reduced, but measurement precision deteriorates due to differential and integral non-linearities
Solution Approach 1:
The patent segments the measurement function into multiple independent time measuring circuits rather than using a single integrated transit time element. This segmentation allows each circuit to be optimized for its specific measurement task with dedicated calibration, reducing the impact of non-linearities and improving overall measurement precision while maintaining manageable complexity through modular design.
Data Source
AI summary
The invention relates to a method for determining a time of a flank in a signal, wherein the method comprises a step of reading the signal and has a master clock rate for operating a digital evaluation unit for evaluating the time of the flank. The method also comprises a step of forming a data word representing the signal, using a deserializer of a SERDES cell, wherein the data word has a plurality of bits, and wherein a sampling clock rate is applied to the SERDES cell for sampling the signal, which sampling clock rate is higher than the master clock rate, wherein one flank or two flanks of the sampling clock rate are used for sampling the signal. Finally, the method comprises a step of determining the time of the flank in the signal using the data word and the master clock rate in the evaluation unit.