SerDes Frequency Doubler for Low-Skew Quarter-Rate Clocking
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Solution Overview
Problem
High-data-rate serializer-deserializer (SerDes) systems face issues with clock skew and increased power consumption due to the transmission of high-frequency clock signals over long distances on integrated circuit dies, leading to unacceptable signal loss and high power consumption.
Innovation Solution
A quarter-rate clock source is used in conjunction with a frequency doubler to generate a half-rate clock signal, reducing skew and power consumption by transmitting a lower frequency signal, which is then doubled to the SerDes system for serialization and deserialization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a high-frequency clock signal is transmitted over long distances on integrated circuit dies, then the data rate can be increased, but clock skew and signal loss increase uncontrollably
Solution Approach 1:
The clock signal transmission is segmented into two stages: first transmitting a lower-frequency quarter-rate clock signal over the long distance, then using frequency doublers at the destination to generate the required high-frequency half-rate clock signal. This segmentation allows the long-distance transmission to occur at a lower frequency where skew and loss are manageable, while still achieving high data rates through local frequency multiplication.
Solution Approach 2:
The frequency doubler acts as an intermediary device that converts the transmitted quarter-rate clock signal into the required half-rate clock signal. By placing the frequency multiplication function at the receiving end rather than transmitting the high-frequency signal directly, the system achieves high data rates without suffering from the skew and loss problems of long-distance high-frequency transmission.
2Productivity
If a high-frequency clock signal is transmitted over long distances, then the data rate can be increased, but power consumption increases substantially
Solution Approach 1:
The power-intensive frequency multiplication operation is segmented and performed locally at the receiving end rather than being distributed throughout the transmission path. Only the low-frequency clock signal needs to be transmitted over the long distance, minimizing power consumption during transmission, while the high-power frequency doubling occurs only at the destination where the clock signal is needed.
Solution Approach 2:
The frequency doubler serves as a power-efficient intermediary by performing frequency multiplication only at the point of need. This eliminates the power consumption associated with transmitting high-frequency signals over long distances, as only the lower-frequency quarter-rate clock signal is transmitted, and the high-frequency signal is generated locally through frequency doubling.
3Length of stationary object
If the clock frequency is reduced to decrease skew and power consumption, then the transmission distance can be increased, but the data rate decreases
Solution Approach 1:
The system changes the frequency parameter dynamically: the clock signal is transmitted at a lower frequency (quarter-rate) over the long distance to minimize skew and power consumption, then the frequency is doubled at the receiving end to achieve the required high data rate. This parameter change allows the system to optimize for both transmission distance and data rate without compromise.
Solution Approach 2:
The data transmission function is segmented into two parts: long-distance transmission of a low-frequency quarter-rate clock signal, and local high-speed serialization/deserialization using frequency-doubled half-rate clock signals. This segmentation allows the system to achieve both long transmission distance and high data rate by performing frequency multiplication only where needed at the endpoints.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces clock skew and power consumption while maintaining reliable data transmission at high data rates, as the lower frequency quarter-rate clock signal is less prone to distortion and requires less power to generate and transmit.
Implementation Method 1
transmitting a quarter-rate clock signal to a frequency doubler. The frequency doubler doubles the quarter-rate clock signal into a half-rate clock signal
Data Source
AI summary
A quarter-rate clock signal is doubled in a frequency doubler to produce a half-rate clock signal used by a serializer/deserializer (SerDes) interface to serialize and deserialize data.