SerDes Gain Calibration Loop for PVT-Stable Linearity

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Solution Overview

Problem

High-speed data communication interfaces face challenges in maintaining gain stage linearity due to variations in process parameters, voltage, and temperature, which affect signal quality and data transmission rates.

Innovation Solution

A calibration circuit with a replica transconductance and transimpedance stage is used to dynamically adjust gain by comparing input and output voltage levels, controlling feedback resistors to minimize voltage differences and ensure consistent amplification across varying conditions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If gain stage operates under varying process parameters, voltage and temperature conditions, then adaptability is improved, but linearity deteriorates

Engineering Contradiction:
Improveadaptability to PVT variationsVSAvoidgain stage linearity
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent employs replica transconductance and transimpedance stages that replicate the main gain stage circuitry. These replica stages are used to generate calibration signals that represent the actual gain stage behavior under varying PVT conditions, enabling dynamic calibration without directly measuring the main signal path.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent implements a calibration loop that uses a comparison circuit to generate difference signals representing voltage level mismatches. These difference signals are fed back through a digital-to-analog converter and summing circuit to dynamically adjust the gain stage parameters, continuously maintaining linearity across PVT variations.

Inventive Principle:
Principle #23Feedback

2Manufacturing precision

If dynamic calibration is implemented to maintain linearity, then manufacturing precision is improved, but device complexity increases

Engineering Contradiction:
Improvegain stage linearityVSAvoidcalibration circuit complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The calibration circuit uses simplified replica versions of the transconductance and transimpedance stages instead of implementing complex direct measurement circuits. These replicas require fewer components while still providing accurate calibration data for the main gain stage.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The calibration system uses the gain stage's own internal circuits (transconductance and transimpedance stages) to generate calibration signals, rather than requiring external calibration equipment. The system calibrates itself using its existing components, reducing the need for additional external calibration hardware.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS20250266797A1Adaptive loop to improve gain stage linearity in serdes
Publication Date: 2025.08.21 QUALCOMM INC
  • US20250266797A1 patent drawing
  • US20250266797A1 patent drawing
  • US20250266797A1 patent drawing

AI summary

A calibration circuit includes a replica transconductance stage that is a replica of a transconductance amplifier in a serializer/deserializer (SerDes) interface and a replica transimpedance stage that is a replica of a transimpedance amplifier in the SerDes interface. The replica transimpedance stage has an input coupled to its output. A comparison circuit is configured to generate a difference signal representative of a difference between voltage levels of an input signal received at an input of the replica transconductance stage and an output signal representative of voltage level at the output of the replica transimpedance stage. Replica feedback resistors are configured to couple an output of the replica transimpedance stage to the input of the replica transconductance stage. The difference signal can be used to select resistance values provided by the replica feedback resistors and by corresponding gain control resistors in the transimpedance amplifier in the SerDes interface.