SerDes Jitter Tolerance BIST Using Embedded Spread Spectrum Clock Generation
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Solution Overview
Problem
Current automated testing equipment (ATE) lacks the capability to effectively generate and control high-bandwidth jitter for rigorous testing of serializer and deserializer (SerDes) devices, leading to inadequate stress testing of clock and data recovery circuits, which can result in devices with marginal performance escaping production tests and causing system failures.
Innovation Solution
A system and method for generating controllable periodic jitter in a serial data stream using a frequency generator and mixers to produce a frequency-modulated clock signal with a local oscillator frequency ranging from 5 MHz to 150 MHz, allowing for realistic self-testing of SerDes devices without external calibration or additional circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ATE loopback testing is used, then testing simplicity is maintained, but jitter generation capability and test rigor are insufficient
Solution Approach 1:
The patent embeds a jitter generation circuit directly within the SerDes device under test, nesting the test function inside the device itself. This allows the device to generate its own jitter signal for self-testing, eliminating the need for external jitter generation equipment while maintaining test rigor.
Solution Approach 2:
The SerDes device performs self-testing by generating and applying jitter to its own data stream through the embedded circuit. The device serves both as the test subject and the test equipment, enabling rigorous jitter tolerance testing without requiring complex external ATE modifications.
2Reliability
If external jitter generation equipment is added to ATE, then jitter testing capability is improved, but cost and system complexity increase
Solution Approach 1:
The embedded jitter generation circuit serves multiple functions: it generates periodic jitter, applies it to the data stream, and enables self-testing. This multi-functional approach eliminates the need for separate external jitter generation equipment, reducing overall system cost and complexity while maintaining full jitter testing capability.
Solution Approach 2:
The device generates and applies its own jitter signal through the embedded circuit, performing self-testing without requiring external calibration or additional test equipment. This self-service capability reduces production testing costs by eliminating the need for expensive external jitter generation hardware.
3Reliability
If PCB trace ISI jitter is used for loopback testing, then some jitter stress is provided, but jitter control and quantification are difficult
Solution Approach 1:
The patent changes the fundamental parameter of jitter generation from passive PCB trace ISI to active periodic jitter injection through an embedded circuit. This allows precise control of jitter amplitude and frequency parameters, enabling accurate measurement and quantification of jitter tolerance performance.
Solution Approach 2:
The patent replaces the mechanical/physical approach of relying on PCB trace characteristics for jitter generation with an electronic control system. The embedded jitter generation circuit uses electronic signal processing to create precisely controllable periodic jitter, substituting uncontrolled physical trace effects with controllable electronic parameter generation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables practical and cost-effective high-bandwidth jitter tolerance testing in high-volume production, ensuring that SerDes devices are thoroughly tested and reducing the risk of system failures by simulating realistic stress conditions on the receiver stage.
Implementation Method 1
The first mixer is configured to mix a fixed frequency clock signal with the in-phase local oscillator signal to output a first mixer output. The second mixer is configured to mix the fixed frequency clock signal with the quadrature local oscillator signal to output a second mixer output.
Data Source
AI summary
A system for controllably generating jitter in a serial data stream includes a frequency generator and first and second mixers. The frequency generator is configured to output in-phase and quadrature local oscillator signals with a local oscillator frequency of at least about 5 MHz. The local oscillator frequency varies between a selectable minimum frequency and a selectable maximum frequency. The first mixer is configured to mix a fixed frequency clock signal with the in-phase local oscillator signal to output a first mixer output. The second mixer is configured to mix the fixed frequency clock signal with the quadrature local oscillator signal to output a second mixer output. An adder is configured to add the first and second mixer outputs to produce a frequency-modulated clock signal with a frequency that is about the sum of the fixed frequency and the local oscillator frequency and includes a periodic jitter.