SerDes Lane Bonding Control for Synchronized Grouped Links

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

When SerDes lanes are grouped, the signal delay from different lanes within the group causes asynchronous reception of signals, leading to inefficiencies in operation.

Innovation Solution

The SerDes lanes are grouped into configurable groups using a lane bonding control module that includes pipe stage flops and pipe stage match modules to synchronize and match the time delays of control signals, ensuring simultaneous reception across the group.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If SerDes lanes are grouped into configurable groups, then operational flexibility and versatility are improved, but signal delay causes asynchronous reception leading to operational inefficiency

Engineering Contradiction:
Improveconfigurable group configurationVSAvoidoperational efficiency
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent applies preliminary action by introducing delay elements to specific SerDes lanes before they receive control signals. This advance compensation for anticipated delays ensures that all lanes within a configurable group receive signals simultaneously, resolving the asynchronous reception problem while maintaining the flexible grouping capability

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the timing parameter of control signals by introducing variable delays to different lanes. By adjusting the delay parameter for each lane based on its specific path characteristics, the system achieves synchronous reception across all lanes in the group, thereby maintaining both versatility and operational efficiency

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If SerDes lanes are grouped together to form bonded links, then device functionality is enhanced, but signal delay from different lanes causes timing asynchrony

Engineering Contradiction:
Improvebonded link configurationVSAvoidsignal timing delay
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The system performs preliminary timing adjustment by inserting delay elements into the signal paths of lanes that would otherwise arrive early. This proactive synchronization ensures that all control signals across bonded lanes arrive at their destinations simultaneously, eliminating timing asynchrony while preserving bonded link functionality

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces delay elements as intermediary components between the control signal source and the SerDes lanes. These intermediaries adjust the timing of signals passing through them, acting as mediators that balance the arrival times of signals across different lanes in the bonded group

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP4629092A1Serdes lane control bonding systems and methods
Publication Date: 2025.10.08 LATTICE SEMICON CORP
  • EP4629092A1 patent drawingFigure 1
  • EP4629092A1 patent drawingFigure 2A
  • EP4629092A1 patent drawingFigure 2B

AI summary

Various techniques are provided to configure serializer / deserializer (SerDes) lanes in one or more SerDes quads into configurable groups using a bonded link. The configuration registers may configure the SerDes lanes into the configurable groups. A lane bonding control module in each SerDes quad may link the signals, including control signals, that travel within each configurable group. To synchronize the control signals, the lane bonding control module may include one or more flops that introduce a fixed time delay for control signals that travel between SerDes quads, and pipe stage match modules that introduce a variable time delay to match the fixed time delay caused by the flops. Once synchronized, the control signals arrive at different SerDes lanes in the configurable group at the same clock cycle.