SerDes Lane Clocking with Independent Data Rates and Low Jitter
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Solution Overview
Problem
Existing serializer/deserializer (SerDes) lanes in physical layer devices face challenges in operating independently at diverse data rates without stringent clocking requirements, as they often rely on high-frequency clock signals that are difficult to generate and manage, leading to issues with quantization noise and jitter performance.
Innovation Solution
A circuit configuration using a common phase-locked loop (PLL) to step-up a low-frequency off-chip reference clock to a higher on-chip frequency, distributing it to fractional-N PLLs, which suppresses modulation noise by increasing its frequency for filtering, and employs a sigma-delta modulator and out-of-band parasitic poles to achieve comparable jitter and phase noise performance to integer-N PLLs, allowing independent data rate operation for each SerDes lane.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a common PLL is used to step-up clock frequency for multiple SerDes lanes, then clock distribution flexibility and lane independence are improved, but quantization noise and jitter performance deteriorate
Solution Approach 1:
The patent divides the clock distribution system into hierarchical segments: a common PLL for frequency synthesis and multiple fractional-N PLLs for individual lane customization. This segmentation allows each lane to have independent frequency control while sharing the common reference, resolving the contradiction between flexibility and performance.
Solution Approach 2:
The patent introduces an intermediary frequency synthesis stage using a common PLL that converts a low-frequency reference clock to a higher intermediate frequency before distributing to fractional-N PLLs. This intermediary step reduces the division ratio required by individual lane PLLs, thereby suppressing quantization noise and improving jitter performance.
2Adaptability or versatility
If fractional-N PLLs are used for independent data rate operation, then lane-by-lane data rate independence is improved, but quantization noise increases
Solution Approach 1:
The patent performs preliminary frequency multiplication in the common PLL before the frequency is distributed to fractional-N PLLs. By pre-increasing the reference frequency, the subsequent division ratios in fractional-N PLLs are reduced, which minimizes quantization noise generation while preserving data rate independence.
3Speed
If high-frequency clock signals are generated for each SerDes lane, then data rate performance is improved, but device complexity and clock management difficulty increase
Solution Approach 1:
The patent merges the frequency synthesis function into a single common PLL that serves all SerDes lanes. Instead of each lane having its own high-frequency clock generator, the common PLL creates a shared high-frequency intermediate clock that is then distributed and individually adjusted by fractional-N PLLs, reducing overall device complexity.
Solution Approach 2:
The common PLL performs multiple functions: it acts as a frequency multiplier for the reference clock, a shared reference source for all fractional-N PLLs, and a noise-filtering stage. This multi-functionality eliminates the need for separate high-frequency clock generators in each lane, simplifying the overall system.
Data Source
AI summary
A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane. The multiple SerDes data lanes may operate at data rates independent from one another. A single low frequency clock is input to the PHY. A frequency of the single low frequency clock is increased via a common integer-N phase-locked loop (PLL) on the PHY to produce a higher frequency clock. Each of the SerDes data lanes is operated, independently, as a fractional-N PLL that employs the higher frequency clock. Use of the common integer-N PLL enables modulation noise of the fractional-N PLLs to be suppressed by moving the modulation noise to higher frequencies where a level of the modulation noise is filtered, avoiding use of high risk noise cancellation techniques.