SerDes Parallelization Using Latches for Multi-Width Output

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Solution Overview

Problem

Serializer/Deserializers (SerDes) consume significant power and are typically designed to output data at a single bus width, which is inefficient for modern high-speed communication networks that require multiple output bus widths.

Innovation Solution

A SerDes circuit that uses an F2 clock to convert data into four data streams, reduces power consumption by converting flops into latches, and employs a round-robin 'fill' mechanism to accommodate multiple output widths (16, 20, 32, and 40 bits) with additional support for a 10-bit mode, allowing for legacy compatibility.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If SerDes is designed to output data at a single bus width, then the device complexity is reduced, but the adaptability to different communication network requirements deteriorates

Engineering Contradiction:

ImproveSerDes design complexityVSAvoidoutput bus width compatibility

Core Design Contradiction:

Device complexityVSAdaptability or versatility

Solution Approach 1:

The SerDes output configuration is made dynamic through a selectable output configuration mechanism that can switch between different bus widths (16-bit, 20-bit, 32-bit, 40-bit) based on operational requirements. This allows the same hardware to adapt to different communication network standards without requiring multiple dedicated designs.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The SerDes is designed with multi-functionality to support multiple output bus widths using a unified architecture. The same core SerDes circuitry can serve different communication standards (16-bit, 20-bit, 32-bit, 40-bit) through configurable output stages, eliminating the need for separate dedicated SerDes instances for each bus width.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Speed

If SerDes operates at high speed to match communication channel requirements, then the communication speed is improved, but the power consumption increases

Engineering Contradiction:

Improvecommunication channel speedVSAvoidSerDes power consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The SerDes data output is segmented into multiple parallel streams (first data stream and second data stream) that can be independently managed. This segmentation allows for more efficient power management by enabling selective activation of data paths and reducing unnecessary switching activity in high-speed operation modes.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The SerDes employs parameter changes by utilizing an F2 clock input that converts data into four data streams, altering the temporal distribution of data transmission. This parameter change enables high-speed communication while managing power consumption through optimized clocking and data streaming patterns.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS9767062B2Low power parallelization to multiple output bus widths

Publication Date: 2017.09.19 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD

AI summary

A Serializer/Deserializer (SerDes) is described with an architecture that simultaneously provides flexibility for many different gear ratios as well as reduced power consumption. The SerDes utilizes latches where flops were previously used to help reduce power consumption, among other things. The SerDes also includes a main register bank with a plurality of sub-banks that can be filled according to any number of different schemes, thereby enabling the SerDes to accommodate different output widths.