SerDes Loopback Switch Fabric for Low Latency Signal Routing

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Solution Overview

Problem

Conventional signal processing apparatuses face significant signal latency in low latency operation modes due to the necessity of serial and parallel data conversions through serializer/deserializer circuits, which cannot be reduced without increasing complexity.

Innovation Solution

The integration of a high-speed serial switch fabric that directly switches and replicates serial signals between ports, utilizing internal loopback signal paths as low latency functional paths, bypassing the need for serial and parallel conversions in certain scenarios, thereby minimizing latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If serializer/deserializer circuits are used for signal conversion between serial and parallel domains, then data processing capability is improved, but signal latency increases significantly

Engineering Contradiction:
Improvedata processing capabilityVSAvoidsignal latency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent extracts the signal conversion function from the main signal path by using dedicated loopback paths that bypass the serializer/deserializer circuits. The loopback paths allow signals to be redirected internally without undergoing serial-parallel conversion, effectively removing the latency-introducing conversion step from the critical low-latency path while preserving data processing capabilities in normal operation mode.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces loopback paths as intermediary channels that mediate between the reception port and transmission port. These intermediary paths provide an alternative route for signals that requires no conversion, thus reducing latency. The switch fabric acts as a mediator that can route signals through either the conventional SerDes path or the direct loopback path depending on the operational requirements.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Loss of time

If internal loopback signal paths are used for low latency operation, then signal latency is reduced, but signal monitoring capability may be lost

Engineering Contradiction:
Improvesignal latencyVSAvoidsignal monitoring capability
Core Design Contradiction:
Loss of timeVSLoss of information

Solution Approach 1:

The patent creates a copy of the incoming signal that can be routed through the loopback path for low-latency transmission. The original signal path through the serializer/deserializer circuits remains intact and can be used for monitoring and processing. This copying approach allows the system to maintain full monitoring capability while simultaneously providing a low-latency path for time-critical signals.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent designs the loopback paths and switch fabric to serve multiple functions: they provide low-latency signal transmission when activated, while the same infrastructure allows monitoring signals to be tapped and routed to processing logic. The switch fabric can dynamically route signals for different purposes (low-latency forwarding, monitoring, processing) making the system multi-functional without requiring separate dedicated paths for each function.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentEP2933728B1Using serdes loopbacks for low latency functional modes with full monitoring capability
Publication Date: 2017.06.28 ADVA OPTICAL NETWORKING SP ZOO
  • EP2933728B1 patent drawingFigure 1
  • EP2933728B1 patent drawingFigure 2
  • EP2933728B1 patent drawingFigure 3

AI summary

An apparatus (1) comprising high speed ports (2) connected via an integrated high speed serial switch fabric (22) and serializer/deserializer circuits to an internal processing logic (6), wherein said high speed serial switch fabric is adapted to switch a serial reception signal received by a high speed port to at least one other high speed port of said apparatus and/or to the serializer/deserializer circuit of the receiving high speed port.