SerDes Multi-Sync Interface for Low-Latency Clock Mismatch Handling

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Solution Overview

Problem

High-speed serializer/deserializer (HSS) interfaces face challenges in maintaining low latency and strong reliability, availability, and serviceability (RAS) characteristics due to frequency and phase differences between sender and receiver clocks, as well as failure modes and extra overhead in data packets, leading to latency penalties and performance degradation.

Innovation Solution

A computer-implemented method that automatically determines the operation mode of a data transmission system, switching between synchronous and asynchronous modes based on performance analyses, and includes diagnosis functionality to diagnose the source of non-synchronous operation, enabling continued operation and reducing complexity in mitigation strategies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If synchronous operation mode is used for HSS data transmission, then data transmission speed and timing alignment are improved, but system reliability deteriorates due to frequency and phase differences between sender and receiver clocks

Engineering Contradiction:
Improvedata transmission speedVSAvoidsystem reliability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The system dynamically transitions between synchronous and asynchronous operation modes based on real-time performance analysis. When frequency or phase differences are detected between sender and receiver clocks, the system switches from synchronous to asynchronous mode to maintain reliability while continuing data transmission.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the operational parameters by switching between different synchronization modes (synchronous, mesochronous, asynchronous) depending on the detected clock alignment conditions. This parameter change allows the system to adapt to varying clock frequency and phase differences between transmitter and receiver.

Inventive Principle:
Principle #35Parameter changes

2Stability of the object's composition

If synchronous operation mode is used, then timing alignment is improved, but latency increases due to failure modes and extra overhead in data packets

Engineering Contradiction:
Improvetiming alignmentVSAvoidlatency
Core Design Contradiction:
Stability of the object's compositionVSLoss of time

Solution Approach 1:

The system dynamically adjusts the operation mode based on performance analysis results. When timing alignment is sufficient, synchronous mode is used for optimal timing. When failures or excessive overhead are detected, the system transitions to asynchronous mode to reduce latency while maintaining acceptable timing alignment through continued operation.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system extracts and analyzes specific performance metrics (frequency differences, phase differences, error rates) to determine when to switch modes. By taking out only the necessary performance analysis functions, the system avoids the full overhead of synchronous operation while maintaining timing alignment when possible.

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If automated mode switching and diagnosis functionality are added, then system reliability and adaptability are improved, but device complexity increases

Engineering Contradiction:
Improvesystem reliabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system performs self-diagnosis and automated mode switching without external intervention. The performance analysis functionality continuously monitors transmission quality and automatically transitions between synchronous and asynchronous modes, eliminating the need for manual configuration or complex external control systems.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The performance analysis module serves multiple functions: detecting frequency differences, detecting phase differences, analyzing error rates, and triggering mode transitions. This multi-functionality reduces the need for separate dedicated circuits for each monitoring task, thereby limiting the increase in device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11646861B2Low-latency, high-availability and high-speed SerDes interface having multiple synchronization modes
Publication Date: 2023.05.09 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US11646861B2 patent drawing
  • US11646861B2 patent drawing
  • US11646861B2 patent drawing

AI summary

A computer-implemented method includes using a transmitter to send data from the transmitter through a plurality of lanes to a receiver using a synchronous operation mode that includes sending the data from the transmitter through the plurality of lanes to the receiver in a synchronous transmission manner that relies on an alignment between a transmitter clock frequency and a receiver clock frequency. A synchronous operation performance analysis (SOPA) is performed during the synchronous operation mode. A switch from the synchronous operation mode to an asynchronous operation mode is made based on a result of performing the SOPA. The asynchronous operation mode includes sending the data from the transmitter through the plurality of lanes to the receiver without requiring alignment between the transmitter clock frequency and the receiver clock frequency.