Master-Slave SerDes Clocking for Automatic Multi-Rate Synchronization
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Solution Overview
Problem
Existing methods for maintaining synchronization among multiple serializer/deserializer (SerDes) circuits in high data throughput applications are costly and inefficient, particularly when requiring different crystal oscillators for various data rates and relying on complex reset signal synchronization.
Innovation Solution
A master-slave interface system where a master SerDes circuit generates a phase-aligned clock signal distributed to slave circuits, with automatic rate detection and data interleaving, allowing dynamic data rate switching and eliminating the need for separate reset signals and data rate control pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an external reference clock is used to synchronize multiple SerDes circuits, then synchronization is achieved at full data rate, but different crystal oscillators are required for each data rate application, increasing system cost
Solution Approach 1:
The patent makes a single reference clock oscillator serve multiple data rate applications by introducing a clock divider in the master SerDes circuit. The clock divider can divide the reference clock by different factors (e.g., 1, 2, 4, 8) to generate master clock signals at different data rates. Slave SerDes circuits automatically detect the master clock rate and adjust their operation accordingly, eliminating the need for multiple crystal oscillators while maintaining synchronization across all data rate applications.
2Productivity
If multiple SerDes circuits each have their own PLL circuits, then high data throughput is achieved, but maintaining synchronization among them increases system complexity
Solution Approach 1:
The patent segments the synchronization function by designating one SerDes circuit as the master and others as slaves. The master SerDes contains the clock divider that generates the master clock signal, while slave SerDes circuits contain frequency detectors that automatically detect the master clock rate. This segmentation simplifies the overall system by centralizing clock generation control while distributing automatic rate detection to all slave circuits, reducing synchronization complexity despite maintaining multiple independent PLL circuits for high throughput.
3Adaptability or versatility
If automatic rate detection is implemented in slave circuits, then dynamic data rate switching is enabled, but additional frequency detection circuitry is required
Solution Approach 1:
The patent implements self-service by enabling slave SerDes circuits to automatically detect the master clock signal frequency and autonomously adjust their own operation to match. Each slave circuit includes a frequency detector that continuously monitors the master clock rate and automatically configures its internal PLL and data rate settings. This eliminates the need for external control signals or manual configuration, allowing dynamic rate switching while keeping the added circuitry minimal and self-managing.
Data Source
AI summary
Methods and apparatus are provided for automatic rate identification and channel synchronization in a master-slave setting for high data throughput applications. An interface is provided for use between a parallel bus and a serial bus. The interface includes a plurality of serializer/deserializer circuits that generate a clock signal, wherein one of the serializer/deserializer circuits is a master circuit generating a master clock signal and the remaining of the serializer/deserializer circuits are slave circuits generating slave clock signals. The master clock signal is substantially phase-aligned to a reference clock and is distributed to the slave circuits. The interface also includes a clock divider associated with the master circuit for selectively generating a master clock signal having one or more lower data rates than the reference clock; and a frequency detector associated with each of the slave circuits for automatically detecting a rate of the master clock signal.