SERDES Equalizer DC Offset Cancellation With Variable Filter Time Constants
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Solution Overview
Problem
In semiconductor integrated circuits, the series switch used to cancel DC offset in high-speed serializer/deserializer (SERDES) systems degrades signal characteristics, and traditional filter circuits with large time constants prolong the time required for DC offset cancellation, especially when dealing with signals of large amplitude.
Innovation Solution
A semiconductor integrated circuit with an equalizer and a processing circuit that adjusts the time constant of filters connected to the equalizer, switching between a small and a larger time constant based on the operational state to efficiently cancel DC offsets, allowing for rapid and accurate offset removal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a series switch is inserted before the equalizer circuit to cancel DC offset, then DC offset cancellation is achieved, but signal characteristics in transmitted data are degraded
Solution Approach 1:
The patent extracts the DC component from the signal path by using a capacitor to block DC while allowing AC signals to pass. Instead of inserting a series switch that degrades signal characteristics, the DC offset is removed by coupling capacitors (e.g., C1, C2) that separate DC and AC components, thereby achieving DC offset cancellation without compromising signal integrity.
Solution Approach 2:
The patent introduces capacitors as intermediary elements between the equalizer circuit and subsequent stages. These capacitors act as mediators that block DC offset while transmitting the AC signal components, thus achieving DC removal without directly interfering with the signal path in a way that would degrade characteristics.
2Reliability
If a filter circuit with a large time constant is placed in series with the equalizer circuit to remove high frequency components, then DC offset cancellation is improved, but the time required to cancel DC offset increases
Solution Approach 1:
The patent employs variable resistors (e.g., R5, R6) that allow the time constant of the filter circuit to be dynamically adjusted. This enables the system to adapt the filtering characteristics based on operational conditions, achieving effective DC offset cancellation without being constrained by a fixed large time constant that would prolong the cancellation process.
Solution Approach 2:
The patent changes the resistance values of resistors in the filter circuit to optimize the time constant. By adjusting parameters such as resistance (through variable resistors) and capacitance (through selectable capacitors), the system achieves efficient DC offset cancellation with an optimized time constant that balances filtering performance and cancellation speed.
Data Source
AI summary
A semiconductor device includes an equalizer for receiving a first signal and outputting a second signal that has been adjusted to compensate for attenuation of the first signal. A filter is connected to the output terminal of the equalizer. A cancellation circuit operates to cancel a DC offset in the output of the equalizer. A processing circuit is configured to control the cancellation circuit to cancel the DC offset according to an output from the filter. The processing circuit sets a time constant for the filter to a first value to permit the cancellation circuit to cancel the DC offset when the equalizer is in a first state, and then sets the time constant to a second value when the equalizer is set to a second state to permit the cancellation circuit to cancel the DC offset when the equalizer is in the second state.