Serializer-Deserializer Parity Checking Across Clock Domains
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Solution Overview
Problem
Existing serializing and deserializing stages in integrated circuits face challenges in real-time error detection and correction during data transmission, particularly in ensuring parity consistency across different clock domains and bit widths, which can lead to undetected errors and hardware failures.
Innovation Solution
The implementation of serializing and deserializing stages that time-multiplex sub-words with error detection codes, such as parity, and selectively replace data bits with error detecting code values to detect errors by synchronizing different clock domains and using parity calculation circuitry to set error indicators, enabling real-time error detection and correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If serializing and deserializing stages are implemented without error detection codes, then device complexity is reduced, but reliability deteriorates due to undetected errors during data transmission
Solution Approach 1:
Error detection codes (parity bits) are calculated and inserted into data words before serialization occurs. This preliminary action allows errors to be detected during or after transmission without requiring complex real-time correction mechanisms, thus improving reliability while controlling device complexity.
Solution Approach 2:
Parity calculation circuitry acts as an intermediary component that computes error detection codes and inserts them into data streams. This separate dedicated circuitry handles the error detection function, allowing the main serializing/deserializing logic to remain relatively simple while still achieving high reliability through the specialized parity checking mechanism.
2Reliability
If parity calculation circuitry is added to detect errors, then reliability improves, but device complexity increases due to additional hardware components
Solution Approach 1:
The system performs self-diagnosis by calculating parity bits and comparing them against received parity data. The serializing and deserializing stages inherently generate and verify their own error detection codes without requiring external monitoring equipment, improving reliability while minimizing additional hardware complexity.
Solution Approach 2:
The parity calculation and error detection functions are merged into the existing serializing and deserializing stage architecture. Rather than adding completely separate error detection systems, the patent integrates parity generation into the data path logic, allowing reliable error detection with minimal incremental hardware complexity.
3Reliability
If error detection is performed across different clock domains, then data transmission reliability improves, but measurement precision deteriorates due to timing synchronization challenges
Solution Approach 1:
The error detection process is segmented into distinct phases: parity calculation in the first clock domain, serialization, then parity verification in the second clock domain. By dividing the error detection function across clock domains rather than attempting simultaneous operation, the system achieves reliable cross-domain error detection while managing timing synchronization through structured phase separation.
Data Source
AI summary
A first serializing stage is provided with a stream of data words composed of sub-words that each have values that associate each of the sub-words with the same error detection code value. For example, the values selected for each sub-word may each be associated with even parity. One or more serializing stages time-multiplex the sub-words into a stream of sub-word sized data. At the serializing stage that receives sub-word sized data stream, the data is checked to determine whether any of the sub-words is no longer associated with the error detection code value. Serializing/deserializing stages are selectively controlled to replace one or more data bits from a word being serialized/deserialized with an error detecting code value (e.g., parity). A subsequent serializing/deserializing stage is enabled to use the inserted error detecting code values and the data in the received words to determine whether an error has occurred.