SerDes Hard IP Passageways Without Redistribution Layer Load
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Solution Overview
Problem
Existing SerDes chiplets face inefficiencies in signal transmission due to the electrical load created by redistribution layers, which limits bandwidth and signal quality, especially at high speeds like 56 Gbps and beyond.
Innovation Solution
The implementation of hard IP blocks with keepout zones beneath the interconnects eliminates the need for redistribution layers, allowing surface interconnects to directly interface with external devices while maintaining low resistive capacitive loads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redistribution layers are used to route signals from SerDes chiplets to external devices, then signal transmission is enabled, but electrical load increases causing bandwidth limitation and signal quality degradation
Solution Approach 1:
The patent extracts and removes the redistribution layer from the signal path by implementing keepout zones that prevent routing layers from occupying the space directly beneath surface interconnects. This eliminates the problematic intermediate structure that was causing electrical load and signal degradation, allowing signals to transmit directly through the substrate without passing through redundant redistribution layers.
Solution Approach 2:
The patent transitions from a planar 2D routing approach to a 3D vertical approach by using through-substrate vias that penetrate the substrate thickness. This dimensional change allows signals to bypass the problematic redistribution layer plane and create direct vertical pathways from surface interconnects to bond pads, reducing the electrical load path length and improving signal integrity.
2Speed
If signals are transmitted through redistribution layers at high speeds (56 Gbps and faster), then data communication is achieved, but resistive capacitive load increases causing eye diagram shrinkage and transmission failure
Solution Approach 1:
The patent removes the redistribution layer from the high-speed signal path by implementing keepout zones that exclude routing from the area beneath surface interconnects. This extraction eliminates the source of resistive capacitive load that was causing energy loss and eye diagram shrinkage at high transmission speeds.
Solution Approach 2:
The patent changes the physical parameters of the signal transmission path by creating direct vertical pathways through the substrate using through-substrate vias. This reduces the path length and electrical load parameters, enabling high-speed signal transmission without the energy loss previously caused by redistribution layers.
3Adaptability or versatility
If through-silicon vias extend outside the SerDes chiplet perimeter to achieve wafer-to-wafer connections, then external device interconnection is enabled, but large resistive capacitive load is created impacting signal quality
Solution Approach 1:
The patent applies local quality by creating keepout zones specifically beneath surface interconnects where through-substrate vias are located. This localized approach maintains the desired wafer-to-wafer interconnection capability while preventing routing from creating additional load in the critical via regions, thereby preserving signal quality in the most important connection points.
Data Source
AI summary
Hard IP blocks, such as SerDes chips, are designed with keepout zones beneath the surface interconnects, the keepout zones being spaces within the chip where there is no circuitry. Connections can be formed between surface interconnects on an under surface of the SerDes chip that faces the host die, and surface interconnects on an upper surface of the Ser Des chip that interfaces without external devices. Accordingly, redistribution layers routing around an outer periphery of the SerDes chip are no longer needed, and the resistive capacitive load remains low so as not to adversely impact transmitted signals.