SerDes PLL Divider Power Sharing for Lower Supply-Induced Jitter
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Solution Overview
Problem
Clock jitter in Serializer/De-serializer (SerDes) circuits degrades data transmission quality due to variations in clock signal periods, which existing technologies have not adequately addressed.
Innovation Solution
The solution involves applying voltage to the frequency divider in the Phase-Locked Loop (PLL) and ensuring signal propagation delays through the frequency divider and transmission circuit are approximately equal, thereby reducing power supply induced jitter and maintaining consistent clock and data delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the frequency divider in the PLL is supplied with a separate clean power supply, then the clock signal quality is improved, but the complexity of the power supply system increases and does not address power supply induced jitter in the transmission circuit
Solution Approach 1:
The patent merges the power supply for the frequency divider with the transmission circuit's power supply (VDDA), eliminating the need for separate clean power supplies. This is achieved by connecting the frequency divider to the same power domain as the transmission circuit, thereby reducing system complexity while maintaining jitter reduction benefits through synchronized power variations.
Solution Approach 2:
The patent converts the harmful effect of power supply noise into a beneficial synchronization mechanism. By allowing the frequency divider to share the same power supply (VDDA) as the transmission circuit, both components experience identical power supply variations, which causes their delays to change in sync. This transforms power supply induced jitter from a harmful factor into a mechanism that maintains relative timing consistency between clock and data paths.
2Stability of the object's composition
If the frequency divider and transmission circuit have different power supplies, then the clock signal is more stable, but power supply induced jitter occurs in the transmission circuit
Solution Approach 1:
The patent creates an equipotential relationship between the frequency divider and transmission circuit by supplying both from the same power domain (VDDA). This ensures that both circuits experience identical power supply voltage variations, making their delay variations synchronized. The relative timing relationship remains stable even though absolute delays vary with power supply conditions.
Solution Approach 2:
The patent changes the power supply parameter from separate stable supplies to a shared dynamic supply (VDDA). This parameter change allows both the frequency divider and transmission circuit to respond identically to power supply variations, transforming the stability problem into a synchronization solution where relative timing is preserved despite absolute delay changes.
3Reliability
If the signal propagation delay through the frequency divider is made equal to the transmission circuit delay, then power supply induced jitter is reduced, but the design complexity of the PLL increases
Solution Approach 1:
The patent implements self-service by allowing the frequency divider to automatically match the transmission circuit's delay characteristics through shared power supply coupling. The identical power supply (VDDA) causes both circuits to experience the same delay variations, automatically achieving delay matching without requiring complex external adjustment mechanisms or additional design efforts.
Solution Approach 2:
The shared power supply creates an implicit feedback mechanism where variations in VDDA simultaneously affect both the frequency divider and transmission circuit. This feedback ensures that delay variations in one circuit are compensated by corresponding variations in the other, maintaining synchronized timing without requiring explicit feedback control circuits.
Data Source
AI summary
In an embodiment of the invention, a frequency divider in a phase-locked loop (PLL) circuit is provided power from the power supply that provides power to a transmission circuit. The PLL is configured to receive a first direct current (DC) reference voltage, a second DC voltage and a reference clock signal. The PLL is configured to generate a transmission clock signal. A transmission circuit is configured to receive the transmission clock signal, the second DC voltage and a data bus where the data bus includes a plurality of data bits in parallel. The transmission circuit transmits data serially.