SerDes PLL Frequency Correction for Bounded Multi-Lane Phase Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing high-speed interfaces for systems like System on Chip (SoC) face challenges in maintaining bounded phase relations across multiple data paths, leading to systematic non-linear errors and impaired Bit-Error-Rate performance, especially at higher data rates.
Innovation Solution
The system employs a digital frequency correction module that supplies data strobe encoded frequency correction signals to independent PLL circuits in the Serializer Deserializer module, using a closed-loop control mechanism to synchronize the transmission frequencies and maintain bounded phase relations across all data paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If phase interpolators with closed-loop control are used for each data-path, then bounded phase relation across all transmitters is maintained, but systematic non-linear error occurs due to intrinsic non-linear behaviour of the interpolation
Solution Approach 1:
The patent replaces the analog phase interpolator mechanism with a digital frequency correction approach. Instead of using phase interpolators that inherently introduce non-linear errors, the invention uses digital frequency correction signals to adjust the output frequency of PLL circuits, thereby maintaining phase relations without the systematic non-linear errors associated with analog interpolation.
Solution Approach 2:
The patent changes the control parameter from direct phase interpolation to frequency correction. By adjusting the frequency of the PLL output clocks through digital correction signals, the system achieves bounded phase relations across data paths without introducing the non-linear errors inherent in phase interpolation methods.
2Area of stationary object
If independent PLL circuits with data strobe encoded frequency correction signals are used, then area and power consumption are reduced, but frequency and phase synchronization across transmitters becomes more challenging
Solution Approach 1:
The patent merges the frequency correction functionality into a unified digital control mechanism that operates across all PLL circuits. By using a common data strobe encoded frequency correction signal format and centralized control logic, the system coordinates multiple independent PLL circuits, achieving both area reduction through independence and precise frequency synchronization through unified digital control.
Solution Approach 2:
The patent implements feedback mechanisms where the digital frequency correction signals are generated based on detected phase errors between write clock and read clock. This closed-loop feedback ensures that even though PLL circuits are independent and space-efficient, they remain precisely synchronized through continuous error detection and correction.
3Reliability
If digital frequency correction module with closed-loop control is implemented, then Bit-Error-Rate performance is enhanced, but device complexity increases
Solution Approach 1:
The patent replaces complex analog phase interpolation circuits with a digital frequency correction module. This substitution simplifies the overall control mechanism by using digital signal processing instead of analog components, thereby enhancing reliability through reduced non-linear errors while keeping the control architecture more manageable through digital implementation.
4Stability of the object's composition
If phase interpolators are used for maintaining phase relations, then bounded phase relation is achieved, but additional noise is injected into the signal
Solution Approach 1:
The patent substitutes analog phase interpolators that inject noise into the signal with a digital frequency correction approach. By controlling PLL output frequencies through digital correction signals rather than analog phase manipulation, the system maintains stable phase relations across data paths without introducing the additional noise characteristic of phase interpolator circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces area and power consumption, minimizes latency, and eliminates additional noise injection, while ensuring accurate frequency and phase updates, thereby enhancing the Bit-Error-Rate performance and data consistency across the system.
Implementation Method 1
respective independent PLL circuits issuing respective PLL clock signals, using as reference a cluster transmitter reference clock common to a respective cluster of transmitters
Data Source
AI summary
An electronic digital system includes a digital core and a Serializer Deserializer module. A FIFO device of the core reads and writes on a set of buses coupled to said Serializer Deserializer module. The Serializer Deserializer module transmits data read from the FIFO architecture device on a set of buses as a corresponding serial signals transmitted by transmitters. The serial signals and corresponding transmitters are logically grouped. The transmitters include PLL circuits generating PLL clocks, using as reference a cluster transmitter reference clock common, to a respective cluster of transmitters controlling a frequency of serialization operation and low frequency clocks obtained by the PLL clocks according to one or more groups corresponding to group of buses.