SerDes Power Throttling by Bit Error Rate Feedback

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Solution Overview

Problem

SerDes links in mobile devices face challenges in reducing power consumption while maintaining acceptable bit error rates, as existing power-saving methods either compromise usability or introduce delays due to the need to re-enable PLL and CDR circuitry.

Innovation Solution

Implementing error detection and correction mechanisms in SerDes devices to dynamically adjust power consumption based on bit error rates, allowing the SerDes links to maintain acceptable error rates without disabling the circuitry, thereby reducing power consumption without compromising link usability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If power is cut to PLL and CDR circuitry to reduce power consumption, then power consumption is reduced, but the interface becomes unusable until circuits are re-enabled causing processor delays

Engineering Contradiction:

Improvepower consumptionVSAvoidinterface usability

Core Design Contradiction:

Use of energy by moving objectVSEase of operation

Solution Approach 1:

The patent implements dynamic power management by adjusting the power state of PLL and CDR circuitry based on detected error rates. When error rates are acceptable, the circuits are throttled or disabled to save power. When error rates exceed thresholds, power is restored to maintain functionality. This dynamic adjustment resolves the contradiction by making the system adaptable to changing conditions rather than statically disabled or enabled.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the power consumption parameter of PLL and CDR circuitry based on error rate measurements. By monitoring bit error rates and adjusting power delivery accordingly, the system transitions between different power states (full power, throttled, disabled) to optimize the trade-off between power consumption and interface usability.

Inventive Principle:

Principle #35Parameter changes

2Use of energy by moving object

If SerDes interface is placed in low-power mode to save power, then power consumption is reduced, but the interface cannot be actively accessed by the processor

Engineering Contradiction:

Improvepower consumptionVSAvoidprocessor memory access

Core Design Contradiction:

Use of energy by moving objectVSProductivity

Solution Approach 1:

The patent employs feedback mechanisms where error rates detected at the receiver end are communicated back to the transmitter and power management logic. This feedback loop enables intelligent decision-making about when to throttle or disable SerDes circuits, ensuring that power-saving actions are taken only when error rates permit, thus maintaining processor productivity while reducing power consumption.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The SerDes interface operates in dynamic power states rather than a fixed low-power mode. The system can transition between active, throttled, and disabled states based on real-time error rate conditions, allowing the interface to be accessible when needed while saving power when acceptable error rates are maintained.

Inventive Principle:

Principle #15Dynamics

3Use of energy by moving object

If signal swing is reduced to minimum necessary level to prevent transmission errors, then power consumption is reduced, but power savings are insufficient for mobile applications

Engineering Contradiction:

Improvepower consumptionVSAvoidtransmission error rate

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The patent applies partial power delivery to SerDes circuits based on actual needs. Instead of always providing full power or completely disabling circuits, the system delivers partial power (throttled state) when error rates are acceptable, achieving intermediate power savings while maintaining sufficient transmission reliability. This partial action approach enables additional power savings beyond minimal signal swing optimization.

Inventive Principle:

Principle #16Partial or excessive action

4Loss of time

If PLL and CDR circuits are kept on to maintain immediate interface availability, then interface responsiveness is improved, but power consumption increases

Engineering Contradiction:

Improveinterface activation delayVSAvoidpower consumption

Core Design Contradiction:

Loss of timeVSUse of energy by moving object

Solution Approach 1:

The patent implements periodic monitoring of error rates and periodic adjustment of power states for PLL and CDR circuitry. Rather than continuously keeping circuits at full power, the system periodically checks error rates and transitions to lower power states when conditions permit, achieving power savings while maintaining readiness to quickly restore full power when errors occur.

Inventive Principle:

Principle #19Periodic action

Data Source

PatentEP2676372B1Serdes power throttling as a function of detected error rate

Publication Date: 2016.10.19 QUALCOMM INC

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AI summary

A system involves a first SerDes link from a first integrated circuit (IC) to a second IC and a second link from the second IC to the first IC. Power consumption settings in circuitry of the first link are adjusted to control power consumption such that the bit error rate of the first link is maintained in a range, where the lower bound of the range is substantially greater than zero. Power consumption settings in circuitry for the second link are adjusted to control power consumption such that the bit error rate of the second link is maintained in range, where the lower bound of the range is substantially greater than zero. In one example, circuitry in the second IC detects errors in the first link and reports back via the second link. The first IC uses the reported information to determine a bit error rate for the first link.