SerDes Receiver Pulse Shaping for CDR and ISI Equalization

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Solution Overview

Problem

Traditional SerDes architectures face limitations in coupling between clock data recovery (CDR) and equalization adaptation, leading to sub-optimal CDR locking points, sensitivity to transmitter settings, and increased complexity due to the dominance of Feed-Forward Equalizers (FFE) in noise and crosstalk correction, which are not effectively addressed by Decision Feedback Equalizers (DFE) due to error propagation and complexity issues.

Innovation Solution

A digital signal processing (DSP) SerDes receiver architecture incorporating a Decision Feedforward Equalizer (DFFE) with integrated CDR and equalization modules, allowing joint auto-adaptation for optimal signal shaping, decoupling CDR and equalization adaptations, and utilizing multi-tap DFFE for both precursor and postcursor ISI correction to achieve symmetric pulse responses and improved noise resilience.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If Feed-Forward Equalizer (FFE) is used for ISI correction, then both precursor and postcursor ISI can be corrected, but noise and crosstalk are amplified

Engineering Contradiction:
ImproveISI correction capabilityVSAvoidnoise and crosstalk amplification
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The equalizer is segmented into two distinct components: FFE for precursor ISI correction and DFE for postcursor ISI correction. This segmentation allows each component to perform its specialized function without the harmful side effects of the other, resolving the contradiction between comprehensive ISI correction and noise amplification.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different equalization strategies are applied to different parts of the ISI problem: FFE is used locally for precursor ISI correction where noise amplification is acceptable, while DFE is used locally for postcursor ISI correction where noise amplification must be avoided. This local quality differentiation optimizes performance for each specific ISI component.

Inventive Principle:
Principle #3Local quality

2Object-affected harmful factors

If Decision Feedback Equalizer (DFE) is used for postcursor ISI correction, then noise is not amplified, but precursor ISI cannot be corrected and error propagation occurs

Engineering Contradiction:
Improvenoise amplification avoidanceVSAvoidprecursor ISI correction and error propagation
Core Design Contradiction:
Object-affected harmful factorsVSReliability

Solution Approach 1:

The equalizer is segmented into two distinct components: FFE for precursor ISI correction and DFE for postcursor ISI correction. This segmentation allows each component to perform its specialized function without the harmful side effects of the other, resolving the contradiction between comprehensive ISI correction and noise amplification.

Inventive Principle:
Principle #1Segmentation

3Measurement precision

If multiple taps of DFE are used for postcursor ISI correction, then correction accuracy improves, but complexity increases exponentially

Engineering Contradiction:
Improvepostcursor ISI correction accuracyVSAvoidimplementation complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The equalizer is segmented into two distinct components: FFE for precursor ISI correction and DFE for postcursor ISI correction. This segmentation allows each component to perform its specialized function without the harmful side effects of the other, resolving the contradiction between comprehensive ISI correction and noise amplification.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10904044B2Serdes receiver with optimized CDR pulse shaping
Publication Date: 2021.01.26 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10904044B2 patent drawing
  • US10904044B2 patent drawing
  • US10904044B2 patent drawing

AI summary

An optimized pulse shaping clock data recovery system is provided that includes a slicer configured to receive a signal and provide an initial set of tentative decisions to a decision feedforward equalizer, where the decision feedforward equalizer provides a fully equalized output signal. The slicer may be incorporated as part of decision feedback equalizer to provide better quality tentative decisions. The clock data recovery system also receives the first output signal that is partially equalized in such a way as to optimally shape it for a clock to sample it at an ideal location by providing an adjustment signal to the analog to digital controller.