SERDES Ratio Alignment for Low Latency Data Transfer

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Solution Overview

Problem

The existing serializer/deserializer (SERDES) components in data transmission systems often require additional clock cycles to transfer data blocks due to non-aligned SERDES ratios with encoding schemes, leading to increased latency, particularly in applications requiring low latency such as high-frequency trading.

Innovation Solution

Configuring the SERDES with a ratio that is a factor of the number of bits in a data block encoded using a specific encoding scheme, such as 64b/66b, to reduce the number of clock cycles needed for data transfer, eliminating extra latency and potentially eliminating the need for additional components like gearbox interfaces.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If the SERDES ratio is configured to match the encoding scheme (e.g., 66-bit block with 64b/66b encoding), then data transfer latency is reduced, but the device complexity increases due to the need for precise ratio configuration

Engineering Contradiction:

Improvedata transfer latencyVSAvoidSERDES configuration complexity

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The patent changes the SERDES ratio parameter to match the encoding scheme. Specifically, when using 64b/66b encoding, the SERDES is configured with a 1:33 ratio (since 66/2 = 33), which allows the 66-bit encoded blocks to be transferred in exactly two clock cycles without requiring additional gearbox interfaces or padding, thereby reducing latency while maintaining compatibility with the encoding scheme.

Inventive Principle:

Principle #35Parameter changes

2Adaptability or versatility

If additional components like gearbox interfaces are used to handle non-aligned SERDES ratios, then adaptability is improved, but device complexity and hardware requirements increase

Engineering Contradiction:

Improvecompatibility with encoding schemesVSAvoidhardware components

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent extracts and eliminates the need for additional gearbox interface components by directly configuring the SERDES ratio to match the encoding scheme. By removing the intermediary gearbox component that was previously needed to handle the mismatch between SERDES ratios and encoding block sizes, the system achieves the same adaptability with simpler hardware.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent makes the SERDES component universally compatible with different encoding schemes by configuring its ratio parameter. Instead of requiring separate gearbox interfaces for different encoding schemes, the SERDES can be directly configured (e.g., 1:33 for 64b/66b, 1:34 for 64b/65b) to work efficiently with each specific encoding scheme, eliminating the need for additional specialized components.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS11178263B2System and a method for controlling timing of processing network data

Publication Date: 2021.11.16 ARISTA NETWORKS INC

AI summary

Embodiments of the invention relate to methods and systems for processing a network data block. One or more embodiments of the invention include receiving network data at a receiver/transmitter comprising a serializer/deserializer (SERDES). One or more embodiments of the invention include identifying, by the PHY, a start of a data block within the network data. One or more embodiments of the invention include performing, by the SERDES and after identifying the start of the data block, a SERDES action to obtain a SERDES data block. In one or more embodiments of the invention, the SERDES action is based on an encoding scheme used in transmission of the network data. One or more embodiments of the invention include also includes transmitting the SERDES data block towards a receiver.